igb: unhide invariant returns (23d87824) · Commits · e / devices / android_kernel_teracube_mt6765

drivers/net/ethernet/intel/igb/e1000_82575.c

+11 −17

Original line number	Original line	Diff line number	Diff line
	@@ -155,7 +155,7 @@ static s32 igb_check_for_link_media_swap(struct e1000_hw *hw)
	ret_val = igb_check_for_link_82575(hw);		ret_val = igb_check_for_link_82575(hw);
	}		}

	return E1000_SUCCESS;		return 0;
	}		}

	/**		/**
	@@ -1004,7 +1004,6 @@ static s32 igb_set_d0_lplu_state_82575(struct e1000_hw *hw, bool active)
	static s32 igb_set_d0_lplu_state_82580(struct e1000_hw *hw, bool active)		static s32 igb_set_d0_lplu_state_82580(struct e1000_hw *hw, bool active)
	{		{
	struct e1000_phy_info *phy = &hw->phy;		struct e1000_phy_info *phy = &hw->phy;
	s32 ret_val = 0;
	u16 data;		u16 data;

	data = rd32(E1000_82580_PHY_POWER_MGMT);		data = rd32(E1000_82580_PHY_POWER_MGMT);
	@@ -1028,7 +1027,7 @@ static s32 igb_set_d0_lplu_state_82580(struct e1000_hw *hw, bool active)
	data &= ~E1000_82580_PM_SPD; }		data &= ~E1000_82580_PM_SPD; }

	wr32(E1000_82580_PHY_POWER_MGMT, data);		wr32(E1000_82580_PHY_POWER_MGMT, data);
	return ret_val;		return 0;
	}		}

	/**		/**
	@@ -1048,7 +1047,6 @@ static s32 igb_set_d0_lplu_state_82580(struct e1000_hw *hw, bool active)
	static s32 igb_set_d3_lplu_state_82580(struct e1000_hw *hw, bool active)		static s32 igb_set_d3_lplu_state_82580(struct e1000_hw *hw, bool active)
	{		{
	struct e1000_phy_info *phy = &hw->phy;		struct e1000_phy_info *phy = &hw->phy;
	s32 ret_val = 0;
	u16 data;		u16 data;

	data = rd32(E1000_82580_PHY_POWER_MGMT);		data = rd32(E1000_82580_PHY_POWER_MGMT);
	@@ -1073,7 +1071,7 @@ static s32 igb_set_d3_lplu_state_82580(struct e1000_hw *hw, bool active)
	}		}

	wr32(E1000_82580_PHY_POWER_MGMT, data);		wr32(E1000_82580_PHY_POWER_MGMT, data);
	return ret_val;		return 0;
	}		}

	/**		/**
	@@ -1199,7 +1197,6 @@ static void igb_release_swfw_sync_82575(struct e1000_hw *hw, u16 mask)
	static s32 igb_get_cfg_done_82575(struct e1000_hw *hw)		static s32 igb_get_cfg_done_82575(struct e1000_hw *hw)
	{		{
	s32 timeout = PHY_CFG_TIMEOUT;		s32 timeout = PHY_CFG_TIMEOUT;
	s32 ret_val = 0;
	u32 mask = E1000_NVM_CFG_DONE_PORT_0;		u32 mask = E1000_NVM_CFG_DONE_PORT_0;

	if (hw->bus.func == 1)		if (hw->bus.func == 1)
	@@ -1223,7 +1220,7 @@ static s32 igb_get_cfg_done_82575(struct e1000_hw *hw)
	(hw->phy.type == e1000_phy_igp_3))		(hw->phy.type == e1000_phy_igp_3))
	igb_phy_init_script_igp3(hw);		igb_phy_init_script_igp3(hw);

	return ret_val;		return 0;
	}		}

	/**		/**
	@@ -1617,7 +1614,7 @@ static s32 igb_setup_serdes_link_82575(struct e1000_hw *hw)
	{		{
	u32 ctrl_ext, ctrl_reg, reg, anadv_reg;		u32 ctrl_ext, ctrl_reg, reg, anadv_reg;
	bool pcs_autoneg;		bool pcs_autoneg;
	s32 ret_val = E1000_SUCCESS;		s32 ret_val = 0;
	u16 data;		u16 data;

	if ((hw->phy.media_type != e1000_media_type_internal_serdes) &&		if ((hw->phy.media_type != e1000_media_type_internal_serdes) &&
	@@ -2518,7 +2515,7 @@ static s32 igb_update_nvm_checksum_i350(struct e1000_hw *hw)
	static s32 __igb_access_emi_reg(struct e1000_hw *hw, u16 address,		static s32 __igb_access_emi_reg(struct e1000_hw *hw, u16 address,
	u16 *data, bool read)		u16 *data, bool read)
	{		{
	s32 ret_val = E1000_SUCCESS;		s32 ret_val = 0;

	ret_val = hw->phy.ops.write_reg(hw, E1000_EMIADD, address);		ret_val = hw->phy.ops.write_reg(hw, E1000_EMIADD, address);
	if (ret_val)		if (ret_val)
	@@ -2552,7 +2549,6 @@ s32 igb_read_emi_reg(struct e1000_hw hw, u16 addr, u16 data)
	**/		**/
	s32 igb_set_eee_i350(struct e1000_hw *hw)		s32 igb_set_eee_i350(struct e1000_hw *hw)
	{		{
	s32 ret_val = 0;
	u32 ipcnfg, eeer;		u32 ipcnfg, eeer;

	if ((hw->mac.type < e1000_i350) \|\|		if ((hw->mac.type < e1000_i350) \|\|
	@@ -2586,7 +2582,7 @@ s32 igb_set_eee_i350(struct e1000_hw *hw)
	rd32(E1000_EEER);		rd32(E1000_EEER);
	out:		out:

	return ret_val;		return 0;
	}		}

	/**		/**
	@@ -2713,7 +2709,6 @@ static const u8 e1000_emc_therm_limit[4] = {
	**/		**/
	static s32 igb_get_thermal_sensor_data_generic(struct e1000_hw *hw)		static s32 igb_get_thermal_sensor_data_generic(struct e1000_hw *hw)
	{		{
	s32 status = E1000_SUCCESS;
	u16 ets_offset;		u16 ets_offset;
	u16 ets_cfg;		u16 ets_cfg;
	u16 ets_sensor;		u16 ets_sensor;
	@@ -2731,7 +2726,7 @@ static s32 igb_get_thermal_sensor_data_generic(struct e1000_hw *hw)
	/* Return the internal sensor only if ETS is unsupported */		/* Return the internal sensor only if ETS is unsupported */
	hw->nvm.ops.read(hw, NVM_ETS_CFG, 1, &ets_offset);		hw->nvm.ops.read(hw, NVM_ETS_CFG, 1, &ets_offset);
	if ((ets_offset == 0x0000) \|\| (ets_offset == 0xFFFF))		if ((ets_offset == 0x0000) \|\| (ets_offset == 0xFFFF))
	return status;		return 0;

	hw->nvm.ops.read(hw, ets_offset, 1, &ets_cfg);		hw->nvm.ops.read(hw, ets_offset, 1, &ets_cfg);
	if (((ets_cfg & NVM_ETS_TYPE_MASK) >> NVM_ETS_TYPE_SHIFT)		if (((ets_cfg & NVM_ETS_TYPE_MASK) >> NVM_ETS_TYPE_SHIFT)
	@@ -2755,7 +2750,7 @@ static s32 igb_get_thermal_sensor_data_generic(struct e1000_hw *hw)
	E1000_I2C_THERMAL_SENSOR_ADDR,		E1000_I2C_THERMAL_SENSOR_ADDR,
	&data->sensor[i].temp);		&data->sensor[i].temp);
	}		}
	return status;		return 0;
	}		}

	/**		/**
	@@ -2767,7 +2762,6 @@ static s32 igb_get_thermal_sensor_data_generic(struct e1000_hw *hw)
	**/		**/
	static s32 igb_init_thermal_sensor_thresh_generic(struct e1000_hw *hw)		static s32 igb_init_thermal_sensor_thresh_generic(struct e1000_hw *hw)
	{		{
	s32 status = E1000_SUCCESS;
	u16 ets_offset;		u16 ets_offset;
	u16 ets_cfg;		u16 ets_cfg;
	u16 ets_sensor;		u16 ets_sensor;
	@@ -2793,7 +2787,7 @@ static s32 igb_init_thermal_sensor_thresh_generic(struct e1000_hw *hw)
	/* Return the internal sensor only if ETS is unsupported */		/* Return the internal sensor only if ETS is unsupported */
	hw->nvm.ops.read(hw, NVM_ETS_CFG, 1, &ets_offset);		hw->nvm.ops.read(hw, NVM_ETS_CFG, 1, &ets_offset);
	if ((ets_offset == 0x0000) \|\| (ets_offset == 0xFFFF))		if ((ets_offset == 0x0000) \|\| (ets_offset == 0xFFFF))
	return status;		return 0;

	hw->nvm.ops.read(hw, ets_offset, 1, &ets_cfg);		hw->nvm.ops.read(hw, ets_offset, 1, &ets_cfg);
	if (((ets_cfg & NVM_ETS_TYPE_MASK) >> NVM_ETS_TYPE_SHIFT)		if (((ets_cfg & NVM_ETS_TYPE_MASK) >> NVM_ETS_TYPE_SHIFT)
	@@ -2824,7 +2818,7 @@ static s32 igb_init_thermal_sensor_thresh_generic(struct e1000_hw *hw)
	low_thresh_delta;		low_thresh_delta;
	}		}
	}		}
	return status;		return 0;
	}		}

	#endif		#endif

drivers/net/ethernet/intel/igb/e1000_defines.h

+0 −1

Original line number	Original line	Diff line number	Diff line
	@@ -459,7 +459,6 @@
	#define E1000_RAH_POOL_1 0x00040000		#define E1000_RAH_POOL_1 0x00040000

	/* Error Codes */		/* Error Codes */
	#define E1000_SUCCESS 0
	#define E1000_ERR_NVM 1		#define E1000_ERR_NVM 1
	#define E1000_ERR_PHY 2		#define E1000_ERR_PHY 2
	#define E1000_ERR_CONFIG 3		#define E1000_ERR_CONFIG 3

drivers/net/ethernet/intel/igb/e1000_i210.c

+43 −43

Original line number	Original line	Diff line number	Diff line
	@@ -97,7 +97,7 @@ static s32 igb_get_hw_semaphore_i210(struct e1000_hw *hw)
	return -E1000_ERR_NVM;		return -E1000_ERR_NVM;
	}		}

	return E1000_SUCCESS;		return 0;
	}		}

	/**		/**
	@@ -139,7 +139,7 @@ s32 igb_acquire_swfw_sync_i210(struct e1000_hw *hw, u16 mask)
	u32 swfw_sync;		u32 swfw_sync;
	u32 swmask = mask;		u32 swmask = mask;
	u32 fwmask = mask << 16;		u32 fwmask = mask << 16;
	s32 ret_val = E1000_SUCCESS;		s32 ret_val = 0;
	s32 i = 0, timeout = 200; /* FIXME: find real value to use here */		s32 i = 0, timeout = 200; /* FIXME: find real value to use here */

	while (i < timeout) {		while (i < timeout) {
	@@ -184,7 +184,7 @@ void igb_release_swfw_sync_i210(struct e1000_hw *hw, u16 mask)
	{		{
	u32 swfw_sync;		u32 swfw_sync;

	while (igb_get_hw_semaphore_i210(hw) != E1000_SUCCESS)		while (igb_get_hw_semaphore_i210(hw))
	; /* Empty */		; /* Empty */

	swfw_sync = rd32(E1000_SW_FW_SYNC);		swfw_sync = rd32(E1000_SW_FW_SYNC);
	@@ -207,7 +207,7 @@ void igb_release_swfw_sync_i210(struct e1000_hw *hw, u16 mask)
	static s32 igb_read_nvm_srrd_i210(struct e1000_hw *hw, u16 offset, u16 words,		static s32 igb_read_nvm_srrd_i210(struct e1000_hw *hw, u16 offset, u16 words,
	u16 *data)		u16 *data)
	{		{
	s32 status = E1000_SUCCESS;		s32 status = 0;
	u16 i, count;		u16 i, count;

	/* We cannot hold synchronization semaphores for too long,		/* We cannot hold synchronization semaphores for too long,
	@@ -217,7 +217,7 @@ static s32 igb_read_nvm_srrd_i210(struct e1000_hw *hw, u16 offset, u16 words,
	for (i = 0; i < words; i += E1000_EERD_EEWR_MAX_COUNT) {		for (i = 0; i < words; i += E1000_EERD_EEWR_MAX_COUNT) {
	count = (words - i) / E1000_EERD_EEWR_MAX_COUNT > 0 ?		count = (words - i) / E1000_EERD_EEWR_MAX_COUNT > 0 ?
	E1000_EERD_EEWR_MAX_COUNT : (words - i);		E1000_EERD_EEWR_MAX_COUNT : (words - i);
	if (hw->nvm.ops.acquire(hw) == E1000_SUCCESS) {		if (!(hw->nvm.ops.acquire(hw))) {
	status = igb_read_nvm_eerd(hw, offset, count,		status = igb_read_nvm_eerd(hw, offset, count,
	data + i);		data + i);
	hw->nvm.ops.release(hw);		hw->nvm.ops.release(hw);
	@@ -225,7 +225,7 @@ static s32 igb_read_nvm_srrd_i210(struct e1000_hw *hw, u16 offset, u16 words,
	status = E1000_ERR_SWFW_SYNC;		status = E1000_ERR_SWFW_SYNC;
	}		}

	if (status != E1000_SUCCESS)		if (status)
	break;		break;
	}		}

	@@ -250,7 +250,7 @@ static s32 igb_write_nvm_srwr(struct e1000_hw *hw, u16 offset, u16 words,
	struct e1000_nvm_info *nvm = &hw->nvm;		struct e1000_nvm_info *nvm = &hw->nvm;
	u32 i, k, eewr = 0;		u32 i, k, eewr = 0;
	u32 attempts = 100000;		u32 attempts = 100000;
	s32 ret_val = E1000_SUCCESS;		s32 ret_val = 0;

	/* A check for invalid values: offset too large, too many words,		/* A check for invalid values: offset too large, too many words,
	* too many words for the offset, and not enough words.		* too many words for the offset, and not enough words.
	@@ -272,13 +272,13 @@ static s32 igb_write_nvm_srwr(struct e1000_hw *hw, u16 offset, u16 words,
	for (k = 0; k < attempts; k++) {		for (k = 0; k < attempts; k++) {
	if (E1000_NVM_RW_REG_DONE &		if (E1000_NVM_RW_REG_DONE &
	rd32(E1000_SRWR)) {		rd32(E1000_SRWR)) {
	ret_val = E1000_SUCCESS;		ret_val = 0;
	break;		break;
	}		}
	udelay(5);		udelay(5);
	}		}

	if (ret_val != E1000_SUCCESS) {		if (ret_val) {
	hw_dbg("Shadow RAM write EEWR timed out\n");		hw_dbg("Shadow RAM write EEWR timed out\n");
	break;		break;
	}		}
	@@ -307,7 +307,7 @@ static s32 igb_write_nvm_srwr(struct e1000_hw *hw, u16 offset, u16 words,
	static s32 igb_write_nvm_srwr_i210(struct e1000_hw *hw, u16 offset, u16 words,		static s32 igb_write_nvm_srwr_i210(struct e1000_hw *hw, u16 offset, u16 words,
	u16 *data)		u16 *data)
	{		{
	s32 status = E1000_SUCCESS;		s32 status = 0;
	u16 i, count;		u16 i, count;

	/* We cannot hold synchronization semaphores for too long,		/* We cannot hold synchronization semaphores for too long,
	@@ -317,7 +317,7 @@ static s32 igb_write_nvm_srwr_i210(struct e1000_hw *hw, u16 offset, u16 words,
	for (i = 0; i < words; i += E1000_EERD_EEWR_MAX_COUNT) {		for (i = 0; i < words; i += E1000_EERD_EEWR_MAX_COUNT) {
	count = (words - i) / E1000_EERD_EEWR_MAX_COUNT > 0 ?		count = (words - i) / E1000_EERD_EEWR_MAX_COUNT > 0 ?
	E1000_EERD_EEWR_MAX_COUNT : (words - i);		E1000_EERD_EEWR_MAX_COUNT : (words - i);
	if (hw->nvm.ops.acquire(hw) == E1000_SUCCESS) {		if (!(hw->nvm.ops.acquire(hw))) {
	status = igb_write_nvm_srwr(hw, offset, count,		status = igb_write_nvm_srwr(hw, offset, count,
	data + i);		data + i);
	hw->nvm.ops.release(hw);		hw->nvm.ops.release(hw);
	@@ -325,7 +325,7 @@ static s32 igb_write_nvm_srwr_i210(struct e1000_hw *hw, u16 offset, u16 words,
	status = E1000_ERR_SWFW_SYNC;		status = E1000_ERR_SWFW_SYNC;
	}		}

	if (status != E1000_SUCCESS)		if (status)
	break;		break;
	}		}

	@@ -364,12 +364,12 @@ static s32 igb_read_invm_word_i210(struct e1000_hw hw, u8 address, u16 data)
	*data = INVM_DWORD_TO_WORD_DATA(invm_dword);		*data = INVM_DWORD_TO_WORD_DATA(invm_dword);
	hw_dbg("Read INVM Word 0x%02x = %x\n",		hw_dbg("Read INVM Word 0x%02x = %x\n",
	address, *data);		address, *data);
	status = E1000_SUCCESS;		status = 0;
	break;		break;
	}		}
	}		}
	}		}
	if (status != E1000_SUCCESS)		if (status)
	hw_dbg("Requested word 0x%02x not found in OTP\n", address);		hw_dbg("Requested word 0x%02x not found in OTP\n", address);
	return status;		return status;
	}		}
	@@ -385,7 +385,7 @@ static s32 igb_read_invm_word_i210(struct e1000_hw hw, u8 address, u16 data)
	static s32 igb_read_invm_i210(struct e1000_hw *hw, u16 offset,		static s32 igb_read_invm_i210(struct e1000_hw *hw, u16 offset,
	u16 words __always_unused, u16 *data)		u16 words __always_unused, u16 *data)
	{		{
	s32 ret_val = E1000_SUCCESS;		s32 ret_val = 0;

	/* Only the MAC addr is required to be present in the iNVM */		/* Only the MAC addr is required to be present in the iNVM */
	switch (offset) {		switch (offset) {
	@@ -395,42 +395,42 @@ static s32 igb_read_invm_i210(struct e1000_hw *hw, u16 offset,
	&data[1]);		&data[1]);
	ret_val \|= igb_read_invm_word_i210(hw, (u8)offset+2,		ret_val \|= igb_read_invm_word_i210(hw, (u8)offset+2,
	&data[2]);		&data[2]);
	if (ret_val != E1000_SUCCESS)		if (ret_val)
	hw_dbg("MAC Addr not found in iNVM\n");		hw_dbg("MAC Addr not found in iNVM\n");
	break;		break;
	case NVM_INIT_CTRL_2:		case NVM_INIT_CTRL_2:
	ret_val = igb_read_invm_word_i210(hw, (u8)offset, data);		ret_val = igb_read_invm_word_i210(hw, (u8)offset, data);
	if (ret_val != E1000_SUCCESS) {		if (ret_val) {
	*data = NVM_INIT_CTRL_2_DEFAULT_I211;		*data = NVM_INIT_CTRL_2_DEFAULT_I211;
	ret_val = E1000_SUCCESS;		ret_val = 0;
	}		}
	break;		break;
	case NVM_INIT_CTRL_4:		case NVM_INIT_CTRL_4:
	ret_val = igb_read_invm_word_i210(hw, (u8)offset, data);		ret_val = igb_read_invm_word_i210(hw, (u8)offset, data);
	if (ret_val != E1000_SUCCESS) {		if (ret_val) {
	*data = NVM_INIT_CTRL_4_DEFAULT_I211;		*data = NVM_INIT_CTRL_4_DEFAULT_I211;
	ret_val = E1000_SUCCESS;		ret_val = 0;
	}		}
	break;		break;
	case NVM_LED_1_CFG:		case NVM_LED_1_CFG:
	ret_val = igb_read_invm_word_i210(hw, (u8)offset, data);		ret_val = igb_read_invm_word_i210(hw, (u8)offset, data);
	if (ret_val != E1000_SUCCESS) {		if (ret_val) {
	*data = NVM_LED_1_CFG_DEFAULT_I211;		*data = NVM_LED_1_CFG_DEFAULT_I211;
	ret_val = E1000_SUCCESS;		ret_val = 0;
	}		}
	break;		break;
	case NVM_LED_0_2_CFG:		case NVM_LED_0_2_CFG:
	ret_val = igb_read_invm_word_i210(hw, (u8)offset, data);		ret_val = igb_read_invm_word_i210(hw, (u8)offset, data);
	if (ret_val != E1000_SUCCESS) {		if (ret_val) {
	*data = NVM_LED_0_2_CFG_DEFAULT_I211;		*data = NVM_LED_0_2_CFG_DEFAULT_I211;
	ret_val = E1000_SUCCESS;		ret_val = 0;
	}		}
	break;		break;
	case NVM_ID_LED_SETTINGS:		case NVM_ID_LED_SETTINGS:
	ret_val = igb_read_invm_word_i210(hw, (u8)offset, data);		ret_val = igb_read_invm_word_i210(hw, (u8)offset, data);
	if (ret_val != E1000_SUCCESS) {		if (ret_val) {
	*data = ID_LED_RESERVED_FFFF;		*data = ID_LED_RESERVED_FFFF;
	ret_val = E1000_SUCCESS;		ret_val = 0;
	}		}
	break;		break;
	case NVM_SUB_DEV_ID:		case NVM_SUB_DEV_ID:
	@@ -486,14 +486,14 @@ s32 igb_read_invm_version(struct e1000_hw *hw,
	/* Check if we have first version location used */		/* Check if we have first version location used */
	if ((i == 1) && ((*record & E1000_INVM_VER_FIELD_ONE) == 0)) {		if ((i == 1) && ((*record & E1000_INVM_VER_FIELD_ONE) == 0)) {
	version = 0;		version = 0;
	status = E1000_SUCCESS;		status = 0;
	break;		break;
	}		}
	/* Check if we have second version location used */		/* Check if we have second version location used */
	else if ((i == 1) &&		else if ((i == 1) &&
	((*record & E1000_INVM_VER_FIELD_TWO) == 0)) {		((*record & E1000_INVM_VER_FIELD_TWO) == 0)) {
	version = (*record & E1000_INVM_VER_FIELD_ONE) >> 3;		version = (*record & E1000_INVM_VER_FIELD_ONE) >> 3;
	status = E1000_SUCCESS;		status = 0;
	break;		break;
	}		}
	/* Check if we have odd version location		/* Check if we have odd version location
	@@ -504,7 +504,7 @@ s32 igb_read_invm_version(struct e1000_hw *hw,
	(i != 1))) {		(i != 1))) {
	version = (*next_record & E1000_INVM_VER_FIELD_TWO)		version = (*next_record & E1000_INVM_VER_FIELD_TWO)
	>> 13;		>> 13;
	status = E1000_SUCCESS;		status = 0;
	break;		break;
	}		}
	/* Check if we have even version location		/* Check if we have even version location
	@@ -513,12 +513,12 @@ s32 igb_read_invm_version(struct e1000_hw *hw,
	else if (((*record & E1000_INVM_VER_FIELD_TWO) == 0) &&		else if (((*record & E1000_INVM_VER_FIELD_TWO) == 0) &&
	((*record & 0x3) == 0)) {		((*record & 0x3) == 0)) {
	version = (*record & E1000_INVM_VER_FIELD_ONE) >> 3;		version = (*record & E1000_INVM_VER_FIELD_ONE) >> 3;
	status = E1000_SUCCESS;		status = 0;
	break;		break;
	}		}
	}		}

	if (status == E1000_SUCCESS) {		if (!status) {
	invm_ver->invm_major = (version & E1000_INVM_MAJOR_MASK)		invm_ver->invm_major = (version & E1000_INVM_MAJOR_MASK)
	>> E1000_INVM_MAJOR_SHIFT;		>> E1000_INVM_MAJOR_SHIFT;
	invm_ver->invm_minor = version & E1000_INVM_MINOR_MASK;		invm_ver->invm_minor = version & E1000_INVM_MINOR_MASK;
	@@ -531,7 +531,7 @@ s32 igb_read_invm_version(struct e1000_hw *hw,
	/* Check if we have image type in first location used */		/* Check if we have image type in first location used */
	if ((i == 1) && ((*record & E1000_INVM_IMGTYPE_FIELD) == 0)) {		if ((i == 1) && ((*record & E1000_INVM_IMGTYPE_FIELD) == 0)) {
	invm_ver->invm_img_type = 0;		invm_ver->invm_img_type = 0;
	status = E1000_SUCCESS;		status = 0;
	break;		break;
	}		}
	/* Check if we have image type in first location used */		/* Check if we have image type in first location used */
	@@ -540,7 +540,7 @@ s32 igb_read_invm_version(struct e1000_hw *hw,
	((((*record & 0x3) != 0) && (i != 1)))) {		((((*record & 0x3) != 0) && (i != 1)))) {
	invm_ver->invm_img_type =		invm_ver->invm_img_type =
	(*next_record & E1000_INVM_IMGTYPE_FIELD) >> 23;		(*next_record & E1000_INVM_IMGTYPE_FIELD) >> 23;
	status = E1000_SUCCESS;		status = 0;
	break;		break;
	}		}
	}		}
	@@ -556,10 +556,10 @@ s32 igb_read_invm_version(struct e1000_hw *hw,
	**/		**/
	static s32 igb_validate_nvm_checksum_i210(struct e1000_hw *hw)		static s32 igb_validate_nvm_checksum_i210(struct e1000_hw *hw)
	{		{
	s32 status = E1000_SUCCESS;		s32 status = 0;
	s32 (read_op_ptr)(struct e1000_hw , u16, u16, u16 *);		s32 (read_op_ptr)(struct e1000_hw , u16, u16, u16 *);

	if (hw->nvm.ops.acquire(hw) == E1000_SUCCESS) {		if (!(hw->nvm.ops.acquire(hw))) {

	/* Replace the read function with semaphore grabbing with		/* Replace the read function with semaphore grabbing with
	* the one that skips this for a while.		* the one that skips this for a while.
	@@ -591,7 +591,7 @@ static s32 igb_validate_nvm_checksum_i210(struct e1000_hw *hw)
	**/		**/
	static s32 igb_update_nvm_checksum_i210(struct e1000_hw *hw)		static s32 igb_update_nvm_checksum_i210(struct e1000_hw *hw)
	{		{
	s32 ret_val = E1000_SUCCESS;		s32 ret_val = 0;
	u16 checksum = 0;		u16 checksum = 0;
	u16 i, nvm_data;		u16 i, nvm_data;

	@@ -600,12 +600,12 @@ static s32 igb_update_nvm_checksum_i210(struct e1000_hw *hw)
	* EEPROM read fails		* EEPROM read fails
	*/		*/
	ret_val = igb_read_nvm_eerd(hw, 0, 1, &nvm_data);		ret_val = igb_read_nvm_eerd(hw, 0, 1, &nvm_data);
	if (ret_val != E1000_SUCCESS) {		if (ret_val) {
	hw_dbg("EEPROM read failed\n");		hw_dbg("EEPROM read failed\n");
	goto out;		goto out;
	}		}

	if (hw->nvm.ops.acquire(hw) == E1000_SUCCESS) {		if (!(hw->nvm.ops.acquire(hw))) {
	/* Do not use hw->nvm.ops.write, hw->nvm.ops.read		/* Do not use hw->nvm.ops.write, hw->nvm.ops.read
	* because we do not want to take the synchronization		* because we do not want to take the synchronization
	* semaphores twice here.		* semaphores twice here.
	@@ -623,7 +623,7 @@ static s32 igb_update_nvm_checksum_i210(struct e1000_hw *hw)
	checksum = (u16) NVM_SUM - checksum;		checksum = (u16) NVM_SUM - checksum;
	ret_val = igb_write_nvm_srwr(hw, NVM_CHECKSUM_REG, 1,		ret_val = igb_write_nvm_srwr(hw, NVM_CHECKSUM_REG, 1,
	&checksum);		&checksum);
	if (ret_val != E1000_SUCCESS) {		if (ret_val) {
	hw->nvm.ops.release(hw);		hw->nvm.ops.release(hw);
	hw_dbg("NVM Write Error while updating checksum.\n");		hw_dbg("NVM Write Error while updating checksum.\n");
	goto out;		goto out;
	@@ -652,7 +652,7 @@ static s32 igb_pool_flash_update_done_i210(struct e1000_hw *hw)
	for (i = 0; i < E1000_FLUDONE_ATTEMPTS; i++) {		for (i = 0; i < E1000_FLUDONE_ATTEMPTS; i++) {
	reg = rd32(E1000_EECD);		reg = rd32(E1000_EECD);
	if (reg & E1000_EECD_FLUDONE_I210) {		if (reg & E1000_EECD_FLUDONE_I210) {
	ret_val = E1000_SUCCESS;		ret_val = 0;
	break;		break;
	}		}
	udelay(5);		udelay(5);
	@@ -685,7 +685,7 @@ bool igb_get_flash_presence_i210(struct e1000_hw *hw)
	**/		**/
	static s32 igb_update_flash_i210(struct e1000_hw *hw)		static s32 igb_update_flash_i210(struct e1000_hw *hw)
	{		{
	s32 ret_val = E1000_SUCCESS;		s32 ret_val = 0;
	u32 flup;		u32 flup;

	ret_val = igb_pool_flash_update_done_i210(hw);		ret_val = igb_pool_flash_update_done_i210(hw);
	@@ -698,7 +698,7 @@ static s32 igb_update_flash_i210(struct e1000_hw *hw)
	wr32(E1000_EECD, flup);		wr32(E1000_EECD, flup);

	ret_val = igb_pool_flash_update_done_i210(hw);		ret_val = igb_pool_flash_update_done_i210(hw);
	if (ret_val == E1000_SUCCESS)		if (ret_val)
	hw_dbg("Flash update complete\n");		hw_dbg("Flash update complete\n");
	else		else
	hw_dbg("Flash update time out\n");		hw_dbg("Flash update time out\n");
	@@ -751,7 +751,7 @@ s32 igb_valid_led_default_i210(struct e1000_hw hw, u16 data)
	static s32 __igb_access_xmdio_reg(struct e1000_hw *hw, u16 address,		static s32 __igb_access_xmdio_reg(struct e1000_hw *hw, u16 address,
	u8 dev_addr, u16 *data, bool read)		u8 dev_addr, u16 *data, bool read)
	{		{
	s32 ret_val = E1000_SUCCESS;		s32 ret_val = 0;

	ret_val = hw->phy.ops.write_reg(hw, E1000_MMDAC, dev_addr);		ret_val = hw->phy.ops.write_reg(hw, E1000_MMDAC, dev_addr);
	if (ret_val)		if (ret_val)

drivers/net/ethernet/intel/igb/igb_ethtool.c

+5 −5

Original line number	Original line	Diff line number	Diff line
	@@ -2738,7 +2738,7 @@ static int igb_get_module_info(struct net_device *netdev,
	{		{
	struct igb_adapter *adapter = netdev_priv(netdev);		struct igb_adapter *adapter = netdev_priv(netdev);
	struct e1000_hw *hw = &adapter->hw;		struct e1000_hw *hw = &adapter->hw;
	u32 status = E1000_SUCCESS;		u32 status = 0;
	u16 sff8472_rev, addr_mode;		u16 sff8472_rev, addr_mode;
	bool page_swap = false;		bool page_swap = false;

	@@ -2748,12 +2748,12 @@ static int igb_get_module_info(struct net_device *netdev,

	/* Check whether we support SFF-8472 or not */		/* Check whether we support SFF-8472 or not */
	status = igb_read_phy_reg_i2c(hw, IGB_SFF_8472_COMP, &sff8472_rev);		status = igb_read_phy_reg_i2c(hw, IGB_SFF_8472_COMP, &sff8472_rev);
	if (status != E1000_SUCCESS)		if (status)
	return -EIO;		return -EIO;

	/* addressing mode is not supported */		/* addressing mode is not supported */
	status = igb_read_phy_reg_i2c(hw, IGB_SFF_8472_SWAP, &addr_mode);		status = igb_read_phy_reg_i2c(hw, IGB_SFF_8472_SWAP, &addr_mode);
	if (status != E1000_SUCCESS)		if (status)
	return -EIO;		return -EIO;

	/* addressing mode is not supported */		/* addressing mode is not supported */
	@@ -2780,7 +2780,7 @@ static int igb_get_module_eeprom(struct net_device *netdev,
	{		{
	struct igb_adapter *adapter = netdev_priv(netdev);		struct igb_adapter *adapter = netdev_priv(netdev);
	struct e1000_hw *hw = &adapter->hw;		struct e1000_hw *hw = &adapter->hw;
	u32 status = E1000_SUCCESS;		u32 status = 0;
	u16 *dataword;		u16 *dataword;
	u16 first_word, last_word;		u16 first_word, last_word;
	int i = 0;		int i = 0;
	@@ -2799,7 +2799,7 @@ static int igb_get_module_eeprom(struct net_device *netdev,
	/* Read EEPROM block, SFF-8079/SFF-8472, word at a time */		/* Read EEPROM block, SFF-8079/SFF-8472, word at a time */
	for (i = 0; i < last_word - first_word + 1; i++) {		for (i = 0; i < last_word - first_word + 1; i++) {
	status = igb_read_phy_reg_i2c(hw, first_word + i, &dataword[i]);		status = igb_read_phy_reg_i2c(hw, first_word + i, &dataword[i]);
	if (status != E1000_SUCCESS) {		if (status) {
	/* Error occurred while reading module */		/* Error occurred while reading module */
	kfree(dataword);		kfree(dataword);
	return -EIO;		return -EIO;

drivers/net/ethernet/intel/igb/igb_main.c

+7 −8

Original line number	Original line	Diff line number	Diff line
	@@ -2199,11 +2199,11 @@ static void igb_init_mas(struct igb_adapter *adapter)
	**/		**/
	static s32 igb_init_i2c(struct igb_adapter *adapter)		static s32 igb_init_i2c(struct igb_adapter *adapter)
	{		{
	s32 status = E1000_SUCCESS;		s32 status = 0;

	/* I2C interface supported on i350 devices */		/* I2C interface supported on i350 devices */
	if (adapter->hw.mac.type != e1000_i350)		if (adapter->hw.mac.type != e1000_i350)
	return E1000_SUCCESS;		return 0;

	/* Initialize the i2c bus which is controlled by the registers.		/* Initialize the i2c bus which is controlled by the registers.
	* This bus will use the i2c_algo_bit structue that implements		* This bus will use the i2c_algo_bit structue that implements
	@@ -7935,7 +7935,7 @@ static int igb_ndo_set_vf_spoofchk(struct net_device *netdev, int vf,
	wr32(reg_offset, reg_val);		wr32(reg_offset, reg_val);

	adapter->vf_data[vf].spoofchk_enabled = setting;		adapter->vf_data[vf].spoofchk_enabled = setting;
	return E1000_SUCCESS;		return 0;
	}		}

	static int igb_ndo_get_vf_config(struct net_device *netdev,		static int igb_ndo_get_vf_config(struct net_device *netdev,
	@@ -8097,8 +8097,7 @@ s32 igb_read_i2c_byte(struct e1000_hw *hw, u8 byte_offset,

	swfw_mask = E1000_SWFW_PHY0_SM;		swfw_mask = E1000_SWFW_PHY0_SM;

	if (hw->mac.ops.acquire_swfw_sync(hw, swfw_mask)		if (hw->mac.ops.acquire_swfw_sync(hw, swfw_mask))
	!= E1000_SUCCESS)
	return E1000_ERR_SWFW_SYNC;		return E1000_ERR_SWFW_SYNC;

	status = i2c_smbus_read_byte_data(this_client, byte_offset);		status = i2c_smbus_read_byte_data(this_client, byte_offset);
	@@ -8108,7 +8107,7 @@ s32 igb_read_i2c_byte(struct e1000_hw *hw, u8 byte_offset,
	return E1000_ERR_I2C;		return E1000_ERR_I2C;
	else {		else {
	*data = status;		*data = status;
	return E1000_SUCCESS;		return 0;
	}		}
	}		}

	@@ -8133,7 +8132,7 @@ s32 igb_write_i2c_byte(struct e1000_hw *hw, u8 byte_offset,
	if (!this_client)		if (!this_client)
	return E1000_ERR_I2C;		return E1000_ERR_I2C;

	if (hw->mac.ops.acquire_swfw_sync(hw, swfw_mask) != E1000_SUCCESS)		if (hw->mac.ops.acquire_swfw_sync(hw, swfw_mask))
	return E1000_ERR_SWFW_SYNC;		return E1000_ERR_SWFW_SYNC;
	status = i2c_smbus_write_byte_data(this_client, byte_offset, data);		status = i2c_smbus_write_byte_data(this_client, byte_offset, data);
	hw->mac.ops.release_swfw_sync(hw, swfw_mask);		hw->mac.ops.release_swfw_sync(hw, swfw_mask);
	@@ -8141,7 +8140,7 @@ s32 igb_write_i2c_byte(struct e1000_hw *hw, u8 byte_offset,
	if (status)		if (status)
	return E1000_ERR_I2C;		return E1000_ERR_I2C;
	else		else
	return E1000_SUCCESS;		return 0;

	}		}