Loading drivers/gpu/drm/nouveau/Makefile +2 −0 Original line number Diff line number Diff line Loading @@ -267,6 +267,7 @@ nouveau-y += core/engine/disp/nvd0.o nouveau-y += core/engine/disp/nve0.o nouveau-y += core/engine/disp/nvf0.o nouveau-y += core/engine/disp/gm107.o nouveau-y += core/engine/disp/gm204.o nouveau-y += core/engine/disp/dacnv50.o nouveau-y += core/engine/disp/dport.o nouveau-y += core/engine/disp/hdanva3.o Loading @@ -279,6 +280,7 @@ nouveau-y += core/engine/disp/piornv50.o nouveau-y += core/engine/disp/sornv50.o nouveau-y += core/engine/disp/sornv94.o nouveau-y += core/engine/disp/sornvd0.o nouveau-y += core/engine/disp/sorgm204.o nouveau-y += core/engine/disp/vga.o nouveau-y += core/engine/fifo/base.o nouveau-y += core/engine/fifo/nv04.o Loading drivers/gpu/drm/nouveau/core/engine/disp/gm204.c 0 → 100644 +113 −0 Original line number Diff line number Diff line /* * Copyright 2012 Red Hat Inc. * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), * to deal in the Software without restriction, including without limitation * the rights to use, copy, modify, merge, publish, distribute, sublicense, * and/or sell copies of the Software, and to permit persons to whom the * Software is furnished to do so, subject to the following conditions: * * The above copyright notice and this permission notice shall be included in * all copies or substantial portions of the Software. * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR * OTHER DEALINGS IN THE SOFTWARE. * * Authors: Ben Skeggs */ #include <engine/software.h> #include <engine/disp.h> #include <nvif/class.h> #include "nv50.h" /******************************************************************************* * Base display object ******************************************************************************/ static struct nouveau_oclass gm204_disp_sclass[] = { { GM204_DISP_CORE_CHANNEL_DMA, &nvd0_disp_mast_ofuncs.base }, { GK110_DISP_BASE_CHANNEL_DMA, &nvd0_disp_sync_ofuncs.base }, { GK104_DISP_OVERLAY_CONTROL_DMA, &nvd0_disp_ovly_ofuncs.base }, { GK104_DISP_OVERLAY, &nvd0_disp_oimm_ofuncs.base }, { GK104_DISP_CURSOR, &nvd0_disp_curs_ofuncs.base }, {} }; static struct nouveau_oclass gm204_disp_base_oclass[] = { { GM204_DISP, &nvd0_disp_base_ofuncs }, {} }; /******************************************************************************* * Display engine implementation ******************************************************************************/ static int gm204_disp_ctor(struct nouveau_object *parent, struct nouveau_object *engine, struct nouveau_oclass *oclass, void *data, u32 size, struct nouveau_object **pobject) { struct nv50_disp_priv *priv; int heads = nv_rd32(parent, 0x022448); int ret; ret = nouveau_disp_create(parent, engine, oclass, heads, "PDISP", "display", &priv); *pobject = nv_object(priv); if (ret) return ret; ret = nvkm_event_init(&nvd0_disp_chan_uevent, 1, 17, &priv->uevent); if (ret) return ret; nv_engine(priv)->sclass = gm204_disp_base_oclass; nv_engine(priv)->cclass = &nv50_disp_cclass; nv_subdev(priv)->intr = nvd0_disp_intr; INIT_WORK(&priv->supervisor, nvd0_disp_intr_supervisor); priv->sclass = gm204_disp_sclass; priv->head.nr = heads; priv->dac.nr = 3; priv->sor.nr = 4; priv->dac.power = nv50_dac_power; priv->dac.sense = nv50_dac_sense; priv->sor.power = nv50_sor_power; priv->sor.hda_eld = nvd0_hda_eld; priv->sor.hdmi = nvd0_hdmi_ctrl; return 0; } struct nouveau_oclass * gm204_disp_outp_sclass[] = { &gm204_sor_dp_impl.base.base, NULL }; struct nouveau_oclass * gm204_disp_oclass = &(struct nv50_disp_impl) { .base.base.handle = NV_ENGINE(DISP, 0x07), .base.base.ofuncs = &(struct nouveau_ofuncs) { .ctor = gm204_disp_ctor, .dtor = _nouveau_disp_dtor, .init = _nouveau_disp_init, .fini = _nouveau_disp_fini, }, .base.vblank = &nvd0_disp_vblank_func, .base.outp = gm204_disp_outp_sclass, .mthd.core = &nve0_disp_mast_mthd_chan, .mthd.base = &nvd0_disp_sync_mthd_chan, .mthd.ovly = &nve0_disp_ovly_mthd_chan, .mthd.prev = -0x020000, .head.scanoutpos = nvd0_disp_base_scanoutpos, }.base.base; drivers/gpu/drm/nouveau/core/engine/disp/nv50.h +3 −0 Original line number Diff line number Diff line Loading @@ -242,6 +242,9 @@ int nv94_sor_dp_lnk_pwr(struct nvkm_output_dp *, int); extern struct nouveau_oclass *nv94_disp_outp_sclass[]; extern struct nvkm_output_dp_impl nvd0_sor_dp_impl; int nvd0_sor_dp_lnk_ctl(struct nvkm_output_dp *, int, int, bool); extern struct nouveau_oclass *nvd0_disp_outp_sclass[]; extern struct nvkm_output_dp_impl gm204_sor_dp_impl; #endif drivers/gpu/drm/nouveau/core/engine/disp/sorgm204.c 0 → 100644 +132 −0 Original line number Diff line number Diff line /* * Copyright 2012 Red Hat Inc. * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), * to deal in the Software without restriction, including without limitation * the rights to use, copy, modify, merge, publish, distribute, sublicense, * and/or sell copies of the Software, and to permit persons to whom the * Software is furnished to do so, subject to the following conditions: * * The above copyright notice and this permission notice shall be included in * all copies or substantial portions of the Software. * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR * OTHER DEALINGS IN THE SOFTWARE. * * Authors: Ben Skeggs */ #include <core/os.h> #include <subdev/bios.h> #include <subdev/bios/dcb.h> #include <subdev/bios/dp.h> #include <subdev/bios/init.h> #include <subdev/timer.h> #include "nv50.h" static inline u32 gm204_sor_soff(struct nvkm_output_dp *outp) { return (ffs(outp->base.info.or) - 1) * 0x800; } static inline u32 gm204_sor_loff(struct nvkm_output_dp *outp) { return gm204_sor_soff(outp) + !(outp->base.info.sorconf.link & 1) * 0x80; } static inline u32 gm204_sor_dp_lane_map(struct nv50_disp_priv *priv, u8 lane) { return lane * 0x08; } static int gm204_sor_dp_pattern(struct nvkm_output_dp *outp, int pattern) { struct nv50_disp_priv *priv = (void *)nouveau_disp(outp); const u32 soff = gm204_sor_soff(outp); const u32 data = 0x01010101 * pattern; if (outp->base.info.sorconf.link & 1) nv_mask(priv, 0x61c110 + soff, 0x0f0f0f0f, data); else nv_mask(priv, 0x61c12c + soff, 0x0f0f0f0f, data); return 0; } static int gm204_sor_dp_lnk_pwr(struct nvkm_output_dp *outp, int nr) { struct nv50_disp_priv *priv = (void *)nouveau_disp(outp); const u32 soff = gm204_sor_soff(outp); const u32 loff = gm204_sor_loff(outp); u32 mask = 0, i; for (i = 0; i < nr; i++) mask |= 1 << (gm204_sor_dp_lane_map(priv, i) >> 3); nv_mask(priv, 0x61c130 + loff, 0x0000000f, mask); nv_mask(priv, 0x61c034 + soff, 0x80000000, 0x80000000); nv_wait(priv, 0x61c034 + soff, 0x80000000, 0x00000000); return 0; } static int gm204_sor_dp_drv_ctl(struct nvkm_output_dp *outp, int ln, int vs, int pe, int pc) { struct nv50_disp_priv *priv = (void *)nouveau_disp(outp); struct nouveau_bios *bios = nouveau_bios(priv); const u32 shift = gm204_sor_dp_lane_map(priv, ln); const u32 loff = gm204_sor_loff(outp); u32 addr, data[4]; u8 ver, hdr, cnt, len; struct nvbios_dpout info; struct nvbios_dpcfg ocfg; addr = nvbios_dpout_match(bios, outp->base.info.hasht, outp->base.info.hashm, &ver, &hdr, &cnt, &len, &info); if (!addr) return -ENODEV; addr = nvbios_dpcfg_match(bios, addr, pc, vs, pe, &ver, &hdr, &cnt, &len, &ocfg); if (!addr) return -EINVAL; data[0] = nv_rd32(priv, 0x61c118 + loff) & ~(0x000000ff << shift); data[1] = nv_rd32(priv, 0x61c120 + loff) & ~(0x000000ff << shift); data[2] = nv_rd32(priv, 0x61c130 + loff); if ((data[2] & 0x0000ff00) < (ocfg.tx_pu << 8) || ln == 0) data[2] = (data[2] & ~0x0000ff00) | (ocfg.tx_pu << 8); nv_wr32(priv, 0x61c118 + loff, data[0] | (ocfg.dc << shift)); nv_wr32(priv, 0x61c120 + loff, data[1] | (ocfg.pe << shift)); nv_wr32(priv, 0x61c130 + loff, data[2] | (ocfg.tx_pu << 8)); data[3] = nv_rd32(priv, 0x61c13c + loff) & ~(0x000000ff << shift); nv_wr32(priv, 0x61c13c + loff, data[3] | (ocfg.pc << shift)); return 0; } struct nvkm_output_dp_impl gm204_sor_dp_impl = { .base.base.handle = DCB_OUTPUT_DP, .base.base.ofuncs = &(struct nouveau_ofuncs) { .ctor = _nvkm_output_dp_ctor, .dtor = _nvkm_output_dp_dtor, .init = _nvkm_output_dp_init, .fini = _nvkm_output_dp_fini, }, .pattern = gm204_sor_dp_pattern, .lnk_pwr = gm204_sor_dp_lnk_pwr, .lnk_ctl = nvd0_sor_dp_lnk_ctl, .drv_ctl = gm204_sor_dp_drv_ctl, }; drivers/gpu/drm/nouveau/core/engine/disp/sornvd0.c +1 −1 Original line number Diff line number Diff line Loading @@ -60,7 +60,7 @@ nvd0_sor_dp_pattern(struct nvkm_output_dp *outp, int pattern) return 0; } static int int nvd0_sor_dp_lnk_ctl(struct nvkm_output_dp *outp, int nr, int bw, bool ef) { struct nv50_disp_priv *priv = (void *)nouveau_disp(outp); Loading Loading
drivers/gpu/drm/nouveau/Makefile +2 −0 Original line number Diff line number Diff line Loading @@ -267,6 +267,7 @@ nouveau-y += core/engine/disp/nvd0.o nouveau-y += core/engine/disp/nve0.o nouveau-y += core/engine/disp/nvf0.o nouveau-y += core/engine/disp/gm107.o nouveau-y += core/engine/disp/gm204.o nouveau-y += core/engine/disp/dacnv50.o nouveau-y += core/engine/disp/dport.o nouveau-y += core/engine/disp/hdanva3.o Loading @@ -279,6 +280,7 @@ nouveau-y += core/engine/disp/piornv50.o nouveau-y += core/engine/disp/sornv50.o nouveau-y += core/engine/disp/sornv94.o nouveau-y += core/engine/disp/sornvd0.o nouveau-y += core/engine/disp/sorgm204.o nouveau-y += core/engine/disp/vga.o nouveau-y += core/engine/fifo/base.o nouveau-y += core/engine/fifo/nv04.o Loading
drivers/gpu/drm/nouveau/core/engine/disp/gm204.c 0 → 100644 +113 −0 Original line number Diff line number Diff line /* * Copyright 2012 Red Hat Inc. * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), * to deal in the Software without restriction, including without limitation * the rights to use, copy, modify, merge, publish, distribute, sublicense, * and/or sell copies of the Software, and to permit persons to whom the * Software is furnished to do so, subject to the following conditions: * * The above copyright notice and this permission notice shall be included in * all copies or substantial portions of the Software. * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR * OTHER DEALINGS IN THE SOFTWARE. * * Authors: Ben Skeggs */ #include <engine/software.h> #include <engine/disp.h> #include <nvif/class.h> #include "nv50.h" /******************************************************************************* * Base display object ******************************************************************************/ static struct nouveau_oclass gm204_disp_sclass[] = { { GM204_DISP_CORE_CHANNEL_DMA, &nvd0_disp_mast_ofuncs.base }, { GK110_DISP_BASE_CHANNEL_DMA, &nvd0_disp_sync_ofuncs.base }, { GK104_DISP_OVERLAY_CONTROL_DMA, &nvd0_disp_ovly_ofuncs.base }, { GK104_DISP_OVERLAY, &nvd0_disp_oimm_ofuncs.base }, { GK104_DISP_CURSOR, &nvd0_disp_curs_ofuncs.base }, {} }; static struct nouveau_oclass gm204_disp_base_oclass[] = { { GM204_DISP, &nvd0_disp_base_ofuncs }, {} }; /******************************************************************************* * Display engine implementation ******************************************************************************/ static int gm204_disp_ctor(struct nouveau_object *parent, struct nouveau_object *engine, struct nouveau_oclass *oclass, void *data, u32 size, struct nouveau_object **pobject) { struct nv50_disp_priv *priv; int heads = nv_rd32(parent, 0x022448); int ret; ret = nouveau_disp_create(parent, engine, oclass, heads, "PDISP", "display", &priv); *pobject = nv_object(priv); if (ret) return ret; ret = nvkm_event_init(&nvd0_disp_chan_uevent, 1, 17, &priv->uevent); if (ret) return ret; nv_engine(priv)->sclass = gm204_disp_base_oclass; nv_engine(priv)->cclass = &nv50_disp_cclass; nv_subdev(priv)->intr = nvd0_disp_intr; INIT_WORK(&priv->supervisor, nvd0_disp_intr_supervisor); priv->sclass = gm204_disp_sclass; priv->head.nr = heads; priv->dac.nr = 3; priv->sor.nr = 4; priv->dac.power = nv50_dac_power; priv->dac.sense = nv50_dac_sense; priv->sor.power = nv50_sor_power; priv->sor.hda_eld = nvd0_hda_eld; priv->sor.hdmi = nvd0_hdmi_ctrl; return 0; } struct nouveau_oclass * gm204_disp_outp_sclass[] = { &gm204_sor_dp_impl.base.base, NULL }; struct nouveau_oclass * gm204_disp_oclass = &(struct nv50_disp_impl) { .base.base.handle = NV_ENGINE(DISP, 0x07), .base.base.ofuncs = &(struct nouveau_ofuncs) { .ctor = gm204_disp_ctor, .dtor = _nouveau_disp_dtor, .init = _nouveau_disp_init, .fini = _nouveau_disp_fini, }, .base.vblank = &nvd0_disp_vblank_func, .base.outp = gm204_disp_outp_sclass, .mthd.core = &nve0_disp_mast_mthd_chan, .mthd.base = &nvd0_disp_sync_mthd_chan, .mthd.ovly = &nve0_disp_ovly_mthd_chan, .mthd.prev = -0x020000, .head.scanoutpos = nvd0_disp_base_scanoutpos, }.base.base;
drivers/gpu/drm/nouveau/core/engine/disp/nv50.h +3 −0 Original line number Diff line number Diff line Loading @@ -242,6 +242,9 @@ int nv94_sor_dp_lnk_pwr(struct nvkm_output_dp *, int); extern struct nouveau_oclass *nv94_disp_outp_sclass[]; extern struct nvkm_output_dp_impl nvd0_sor_dp_impl; int nvd0_sor_dp_lnk_ctl(struct nvkm_output_dp *, int, int, bool); extern struct nouveau_oclass *nvd0_disp_outp_sclass[]; extern struct nvkm_output_dp_impl gm204_sor_dp_impl; #endif
drivers/gpu/drm/nouveau/core/engine/disp/sorgm204.c 0 → 100644 +132 −0 Original line number Diff line number Diff line /* * Copyright 2012 Red Hat Inc. * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), * to deal in the Software without restriction, including without limitation * the rights to use, copy, modify, merge, publish, distribute, sublicense, * and/or sell copies of the Software, and to permit persons to whom the * Software is furnished to do so, subject to the following conditions: * * The above copyright notice and this permission notice shall be included in * all copies or substantial portions of the Software. * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR * OTHER DEALINGS IN THE SOFTWARE. * * Authors: Ben Skeggs */ #include <core/os.h> #include <subdev/bios.h> #include <subdev/bios/dcb.h> #include <subdev/bios/dp.h> #include <subdev/bios/init.h> #include <subdev/timer.h> #include "nv50.h" static inline u32 gm204_sor_soff(struct nvkm_output_dp *outp) { return (ffs(outp->base.info.or) - 1) * 0x800; } static inline u32 gm204_sor_loff(struct nvkm_output_dp *outp) { return gm204_sor_soff(outp) + !(outp->base.info.sorconf.link & 1) * 0x80; } static inline u32 gm204_sor_dp_lane_map(struct nv50_disp_priv *priv, u8 lane) { return lane * 0x08; } static int gm204_sor_dp_pattern(struct nvkm_output_dp *outp, int pattern) { struct nv50_disp_priv *priv = (void *)nouveau_disp(outp); const u32 soff = gm204_sor_soff(outp); const u32 data = 0x01010101 * pattern; if (outp->base.info.sorconf.link & 1) nv_mask(priv, 0x61c110 + soff, 0x0f0f0f0f, data); else nv_mask(priv, 0x61c12c + soff, 0x0f0f0f0f, data); return 0; } static int gm204_sor_dp_lnk_pwr(struct nvkm_output_dp *outp, int nr) { struct nv50_disp_priv *priv = (void *)nouveau_disp(outp); const u32 soff = gm204_sor_soff(outp); const u32 loff = gm204_sor_loff(outp); u32 mask = 0, i; for (i = 0; i < nr; i++) mask |= 1 << (gm204_sor_dp_lane_map(priv, i) >> 3); nv_mask(priv, 0x61c130 + loff, 0x0000000f, mask); nv_mask(priv, 0x61c034 + soff, 0x80000000, 0x80000000); nv_wait(priv, 0x61c034 + soff, 0x80000000, 0x00000000); return 0; } static int gm204_sor_dp_drv_ctl(struct nvkm_output_dp *outp, int ln, int vs, int pe, int pc) { struct nv50_disp_priv *priv = (void *)nouveau_disp(outp); struct nouveau_bios *bios = nouveau_bios(priv); const u32 shift = gm204_sor_dp_lane_map(priv, ln); const u32 loff = gm204_sor_loff(outp); u32 addr, data[4]; u8 ver, hdr, cnt, len; struct nvbios_dpout info; struct nvbios_dpcfg ocfg; addr = nvbios_dpout_match(bios, outp->base.info.hasht, outp->base.info.hashm, &ver, &hdr, &cnt, &len, &info); if (!addr) return -ENODEV; addr = nvbios_dpcfg_match(bios, addr, pc, vs, pe, &ver, &hdr, &cnt, &len, &ocfg); if (!addr) return -EINVAL; data[0] = nv_rd32(priv, 0x61c118 + loff) & ~(0x000000ff << shift); data[1] = nv_rd32(priv, 0x61c120 + loff) & ~(0x000000ff << shift); data[2] = nv_rd32(priv, 0x61c130 + loff); if ((data[2] & 0x0000ff00) < (ocfg.tx_pu << 8) || ln == 0) data[2] = (data[2] & ~0x0000ff00) | (ocfg.tx_pu << 8); nv_wr32(priv, 0x61c118 + loff, data[0] | (ocfg.dc << shift)); nv_wr32(priv, 0x61c120 + loff, data[1] | (ocfg.pe << shift)); nv_wr32(priv, 0x61c130 + loff, data[2] | (ocfg.tx_pu << 8)); data[3] = nv_rd32(priv, 0x61c13c + loff) & ~(0x000000ff << shift); nv_wr32(priv, 0x61c13c + loff, data[3] | (ocfg.pc << shift)); return 0; } struct nvkm_output_dp_impl gm204_sor_dp_impl = { .base.base.handle = DCB_OUTPUT_DP, .base.base.ofuncs = &(struct nouveau_ofuncs) { .ctor = _nvkm_output_dp_ctor, .dtor = _nvkm_output_dp_dtor, .init = _nvkm_output_dp_init, .fini = _nvkm_output_dp_fini, }, .pattern = gm204_sor_dp_pattern, .lnk_pwr = gm204_sor_dp_lnk_pwr, .lnk_ctl = nvd0_sor_dp_lnk_ctl, .drv_ctl = gm204_sor_dp_drv_ctl, };
drivers/gpu/drm/nouveau/core/engine/disp/sornvd0.c +1 −1 Original line number Diff line number Diff line Loading @@ -60,7 +60,7 @@ nvd0_sor_dp_pattern(struct nvkm_output_dp *outp, int pattern) return 0; } static int int nvd0_sor_dp_lnk_ctl(struct nvkm_output_dp *outp, int nr, int bw, bool ef) { struct nv50_disp_priv *priv = (void *)nouveau_disp(outp); Loading
Ben Skeggs <bskeggs@redhat.com>Ben Skeggs <bskeggs@redhat.com>