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Commit 1f737ffa authored by Jerome Brunet's avatar Jerome Brunet Committed by Neil Armstrong
Browse files

clk: meson: mpll: fix mpll0 fractional part ignored 



mpll0 clock is special compared to the other mplls. It needs another
bit (ssen) to be set to activate the fractional part the mpll divider

Fixes: 007e6e5c ("clk: meson: mpll: add rw operation")
Signed-off-by: default avatarJerome Brunet <jbrunet@baylibre.com>
Signed-off-by: default avatarNeil Armstrong <narmstrong@baylibre.com>
parent 5771a8c0

drivers/clk/meson/clk-mpll.c

+7 −0
Original line number Diff line number Diff line
@@ -161,6 +161,13 @@ static int mpll_set_rate(struct clk_hw *hw, 
	reg = PARM_SET(p->width, p->shift, reg, 1);

	writel(reg, mpll->base + p->reg_off);



	p = &mpll->ssen;

	if (p->width != 0) {

		reg = readl(mpll->base + p->reg_off);

		reg = PARM_SET(p->width, p->shift, reg, 1);

		writel(reg, mpll->base + p->reg_off);

	}



	p = &mpll->n2;

	reg = readl(mpll->base + p->reg_off);

	reg = PARM_SET(p->width, p->shift, reg, n2);

drivers/clk/meson/clkc.h

+1 −0
Original line number Diff line number Diff line
@@ -118,6 +118,7 @@ struct meson_clk_mpll { 
	struct parm sdm_en;

	struct parm n2;

	struct parm en;

	struct parm ssen;

	spinlock_t *lock;

};

drivers/clk/meson/gxbb.c

+5 −0
Original line number Diff line number Diff line
@@ -528,6 +528,11 @@ static struct meson_clk_mpll gxbb_mpll0 = { 
		.shift   = 14,

		.width	 = 1,

	},

	.ssen = {

		.reg_off = HHI_MPLL_CNTL,

		.shift   = 25,

		.width	 = 1,

	},

	.lock = &clk_lock,

	.hw.init = &(struct clk_init_data){

		.name = "mpll0",

drivers/clk/meson/meson8b.c

+5 −0
Original line number Diff line number Diff line
@@ -267,6 +267,11 @@ static struct meson_clk_mpll meson8b_mpll0 = { 
		.shift   = 14,

		.width   = 1,

	},

	.ssen = {

		.reg_off = HHI_MPLL_CNTL,

		.shift   = 25,

		.width   = 1,

	},

	.lock = &clk_lock,

	.hw.init = &(struct clk_init_data){

		.name = "mpll0",