Merge branch 'master' of git://git.kernel.org/pub/scm/linux/kernel/git/jkirsher/next-queue (1ebd08a7) · Commits · e / devices / android_kernel_teracube_mt6765

drivers/net/ethernet/intel/e1000e/ich8lan.h

+2 −2

Original line number	Original line	Diff line number	Diff line
	@@ -113,7 +113,7 @@
	#define NVM_SIZE_MULTIPLIER 4096 /multiplier for NVMS field /		#define NVM_SIZE_MULTIPLIER 4096 /multiplier for NVMS field /
	#define E1000_FLASH_BASE_ADDR 0xE000 /offset of NVM access regs /		#define E1000_FLASH_BASE_ADDR 0xE000 /offset of NVM access regs /
	#define E1000_CTRL_EXT_NVMVS 0x3 /NVM valid sector /		#define E1000_CTRL_EXT_NVMVS 0x3 /NVM valid sector /
			#define E1000_TARC0_CB_MULTIQ_3_REQ (1 << 28 \| 1 << 29)
	#define PCIE_ICH8_SNOOP_ALL PCIE_NO_SNOOP_ALL		#define PCIE_ICH8_SNOOP_ALL PCIE_NO_SNOOP_ALL

	#define E1000_ICH_RAR_ENTRIES 7		#define E1000_ICH_RAR_ENTRIES 7

drivers/net/ethernet/intel/e1000e/netdev.c

+51 −13

Original line number	Original line	Diff line number	Diff line
	@@ -48,7 +48,7 @@

	#define DRV_EXTRAVERSION "-k"		#define DRV_EXTRAVERSION "-k"

	#define DRV_VERSION "3.2.5" DRV_EXTRAVERSION		#define DRV_VERSION "3.2.6" DRV_EXTRAVERSION
	char e1000e_driver_name[] = "e1000e";		char e1000e_driver_name[] = "e1000e";
	const char e1000e_driver_version[] = DRV_VERSION;		const char e1000e_driver_version[] = DRV_VERSION;

	@@ -4280,18 +4280,29 @@ static cycle_t e1000e_cyclecounter_read(const struct cyclecounter *cc)
	struct e1000_adapter *adapter = container_of(cc, struct e1000_adapter,		struct e1000_adapter *adapter = container_of(cc, struct e1000_adapter,
	cc);		cc);
	struct e1000_hw *hw = &adapter->hw;		struct e1000_hw *hw = &adapter->hw;
			u32 systimel_1, systimel_2, systimeh;
	cycle_t systim, systim_next;		cycle_t systim, systim_next;
	/* SYSTIMH latching upon SYSTIML read does not work well. To fix that		/* SYSTIMH latching upon SYSTIML read does not work well.
	* we don't want to allow overflow of SYSTIML and a change to SYSTIMH		* This means that if SYSTIML overflows after we read it but before
	* to occur between reads, so if we read a vale close to overflow, we		* we read SYSTIMH, the value of SYSTIMH has been incremented and we
	* wait for overflow to occur and read both registers when its safe.		* will experience a huge non linear increment in the systime value
			* to fix that we test for overflow and if true, we re-read systime.
			*/
			systimel_1 = er32(SYSTIML);
			systimeh = er32(SYSTIMH);
			systimel_2 = er32(SYSTIML);
			/* Check for overflow. If there was no overflow, use the values */
			if (systimel_1 < systimel_2) {
			systim = (cycle_t)systimel_1;
			systim \|= (cycle_t)systimeh << 32;
			} else {
			/* There was an overflow, read again SYSTIMH, and use
			* systimel_2
	*/		*/
	u32 systim_overflow_latch_fix = 0x3FFFFFFF;		systimeh = er32(SYSTIMH);
			systim = (cycle_t)systimel_2;
	do {		systim \|= (cycle_t)systimeh << 32;
	systim = (cycle_t)er32(SYSTIML);		}
	} while (systim > systim_overflow_latch_fix);
	systim \|= (cycle_t)er32(SYSTIMH) << 32;

	if ((hw->mac.type == e1000_82574) \|\| (hw->mac.type == e1000_82583)) {		if ((hw->mac.type == e1000_82574) \|\| (hw->mac.type == e1000_82583)) {
	u64 incvalue, time_delta, rem, temp;		u64 incvalue, time_delta, rem, temp;
	@@ -6317,6 +6328,33 @@ static int __e1000_shutdown(struct pci_dev *pdev, bool runtime)
	return retval;		return retval;
	}		}

			/* Ensure that the appropriate bits are set in LPI_CTRL
			* for EEE in Sx
			*/
			if ((hw->phy.type >= e1000_phy_i217) &&
			adapter->eee_advert && hw->dev_spec.ich8lan.eee_lp_ability) {
			u16 lpi_ctrl = 0;

			retval = hw->phy.ops.acquire(hw);
			if (!retval) {
			retval = e1e_rphy_locked(hw, I82579_LPI_CTRL,
			&lpi_ctrl);
			if (!retval) {
			if (adapter->eee_advert &
			hw->dev_spec.ich8lan.eee_lp_ability &
			I82579_EEE_100_SUPPORTED)
			lpi_ctrl \|= I82579_LPI_CTRL_100_ENABLE;
			if (adapter->eee_advert &
			hw->dev_spec.ich8lan.eee_lp_ability &
			I82579_EEE_1000_SUPPORTED)
			lpi_ctrl \|= I82579_LPI_CTRL_1000_ENABLE;

			retval = e1e_wphy_locked(hw, I82579_LPI_CTRL,
			lpi_ctrl);
			}
			}
			hw->phy.ops.release(hw);
			}

	/* Release control of h/w to f/w. If f/w is AMT enabled, this		/* Release control of h/w to f/w. If f/w is AMT enabled, this
	* would have already happened in close and is redundant.		* would have already happened in close and is redundant.
	@@ -6466,7 +6504,7 @@ static int __e1000_resume(struct pci_dev *pdev)
	if (adapter->flags2 & FLAG2_DISABLE_ASPM_L1)		if (adapter->flags2 & FLAG2_DISABLE_ASPM_L1)
	aspm_disable_flag \|= PCIE_LINK_STATE_L1;		aspm_disable_flag \|= PCIE_LINK_STATE_L1;
	if (aspm_disable_flag)		if (aspm_disable_flag)
	e1000e_disable_aspm_locked(pdev, aspm_disable_flag);		e1000e_disable_aspm(pdev, aspm_disable_flag);

	pci_set_master(pdev);		pci_set_master(pdev);

	@@ -6744,7 +6782,7 @@ static pci_ers_result_t e1000_io_slot_reset(struct pci_dev *pdev)
	if (adapter->flags2 & FLAG2_DISABLE_ASPM_L1)		if (adapter->flags2 & FLAG2_DISABLE_ASPM_L1)
	aspm_disable_flag \|= PCIE_LINK_STATE_L1;		aspm_disable_flag \|= PCIE_LINK_STATE_L1;
	if (aspm_disable_flag)		if (aspm_disable_flag)
	e1000e_disable_aspm(pdev, aspm_disable_flag);		e1000e_disable_aspm_locked(pdev, aspm_disable_flag);

	err = pci_enable_device_mem(pdev);		err = pci_enable_device_mem(pdev);
	if (err) {		if (err) {

drivers/net/ethernet/intel/e1000e/regs.h

+2 −3

Original line number	Original line	Diff line number	Diff line
	@@ -125,7 +125,6 @@
	(0x054E4 + ((_i - 16) * 8)))		(0x054E4 + ((_i - 16) * 8)))
	#define E1000_SHRAL(_i) (0x05438 + ((_i) * 8))		#define E1000_SHRAL(_i) (0x05438 + ((_i) * 8))
	#define E1000_SHRAH(_i) (0x0543C + ((_i) * 8))		#define E1000_SHRAH(_i) (0x0543C + ((_i) * 8))
	#define E1000_TARC0_CB_MULTIQ_3_REQ (1 << 28 \| 1 << 29)
	#define E1000_TDFH 0x03410 /* Tx Data FIFO Head - RW */		#define E1000_TDFH 0x03410 /* Tx Data FIFO Head - RW */
	#define E1000_TDFT 0x03418 /* Tx Data FIFO Tail - RW */		#define E1000_TDFT 0x03418 /* Tx Data FIFO Tail - RW */
	#define E1000_TDFHS 0x03420 /* Tx Data FIFO Head Saved - RW */		#define E1000_TDFHS 0x03420 /* Tx Data FIFO Head Saved - RW */

drivers/net/ethernet/intel/i40e/i40e.h

+13 −2

Original line number	Original line	Diff line number	Diff line
	@@ -79,10 +79,13 @@
	#define I40E_MIN_MSIX 2		#define I40E_MIN_MSIX 2
	#define I40E_DEFAULT_NUM_VMDQ_VSI 8 /* max 256 VSIs */		#define I40E_DEFAULT_NUM_VMDQ_VSI 8 /* max 256 VSIs */
	#define I40E_MIN_VSI_ALLOC 51 /* LAN, ATR, FCOE, 32 VF, 16 VMDQ */		#define I40E_MIN_VSI_ALLOC 51 /* LAN, ATR, FCOE, 32 VF, 16 VMDQ */
	#define I40E_DEFAULT_QUEUES_PER_VMDQ 2 /* max 16 qps */		/* max 16 qps */
			#define i40e_default_queues_per_vmdq(pf) \
			(((pf)->flags & I40E_FLAG_RSS_AQ_CAPABLE) ? 4 : 1)
	#define I40E_DEFAULT_QUEUES_PER_VF 4		#define I40E_DEFAULT_QUEUES_PER_VF 4
	#define I40E_DEFAULT_QUEUES_PER_TC 1 /* should be a power of 2 */		#define I40E_DEFAULT_QUEUES_PER_TC 1 /* should be a power of 2 */
	#define I40E_MAX_QUEUES_PER_TC 64 /* should be a power of 2 */		#define i40e_pf_get_max_q_per_tc(pf) \
			(((pf)->flags & I40E_FLAG_128_QP_RSS_CAPABLE) ? 128 : 64)
	#define I40E_FDIR_RING 0		#define I40E_FDIR_RING 0
	#define I40E_FDIR_RING_COUNT 32		#define I40E_FDIR_RING_COUNT 32
	#ifdef I40E_FCOE		#ifdef I40E_FCOE
	@@ -298,6 +301,7 @@ struct i40e_pf {
	#define I40E_FLAG_VMDQ_ENABLED BIT_ULL(7)		#define I40E_FLAG_VMDQ_ENABLED BIT_ULL(7)
	#define I40E_FLAG_FDIR_REQUIRES_REINIT BIT_ULL(8)		#define I40E_FLAG_FDIR_REQUIRES_REINIT BIT_ULL(8)
	#define I40E_FLAG_NEED_LINK_UPDATE BIT_ULL(9)		#define I40E_FLAG_NEED_LINK_UPDATE BIT_ULL(9)
			#define I40E_FLAG_IWARP_ENABLED BIT_ULL(10)
	#ifdef I40E_FCOE		#ifdef I40E_FCOE
	#define I40E_FLAG_FCOE_ENABLED BIT_ULL(11)		#define I40E_FLAG_FCOE_ENABLED BIT_ULL(11)
	#endif /* I40E_FCOE */		#endif /* I40E_FCOE */
	@@ -318,6 +322,12 @@ struct i40e_pf {
	#endif		#endif
	#define I40E_FLAG_PORT_ID_VALID BIT_ULL(28)		#define I40E_FLAG_PORT_ID_VALID BIT_ULL(28)
	#define I40E_FLAG_DCB_CAPABLE BIT_ULL(29)		#define I40E_FLAG_DCB_CAPABLE BIT_ULL(29)
			#define I40E_FLAG_RSS_AQ_CAPABLE BIT_ULL(31)
			#define I40E_FLAG_HW_ATR_EVICT_CAPABLE BIT_ULL(32)
			#define I40E_FLAG_OUTER_UDP_CSUM_CAPABLE BIT_ULL(33)
			#define I40E_FLAG_128_QP_RSS_CAPABLE BIT_ULL(34)
			#define I40E_FLAG_WB_ON_ITR_CAPABLE BIT_ULL(35)
			#define I40E_FLAG_MULTIPLE_TCP_UDP_RSS_PCTYPE BIT_ULL(38)
	#define I40E_FLAG_VEB_MODE_ENABLED BIT_ULL(40)		#define I40E_FLAG_VEB_MODE_ENABLED BIT_ULL(40)

	/* tracks features that get auto disabled by errors */		/* tracks features that get auto disabled by errors */
	@@ -550,6 +560,7 @@ struct i40e_q_vector {
	cpumask_t affinity_mask;		cpumask_t affinity_mask;
	struct rcu_head rcu; /* to avoid race with update stats on free */		struct rcu_head rcu; /* to avoid race with update stats on free */
	char name[I40E_INT_NAME_STR_LEN];		char name[I40E_INT_NAME_STR_LEN];
			bool arm_wb_state;
	} ____cacheline_internodealigned_in_smp;		} ____cacheline_internodealigned_in_smp;

	/* lan device */		/* lan device */

drivers/net/ethernet/intel/i40e/i40e_adminq_cmd.h

+48 −0

Original line number	Original line	Diff line number	Diff line
	@@ -257,6 +257,10 @@ enum i40e_admin_queue_opc {
	/* Tunnel commands */		/* Tunnel commands */
	i40e_aqc_opc_add_udp_tunnel = 0x0B00,		i40e_aqc_opc_add_udp_tunnel = 0x0B00,
	i40e_aqc_opc_del_udp_tunnel = 0x0B01,		i40e_aqc_opc_del_udp_tunnel = 0x0B01,
			i40e_aqc_opc_set_rss_key = 0x0B02,
			i40e_aqc_opc_set_rss_lut = 0x0B03,
			i40e_aqc_opc_get_rss_key = 0x0B04,
			i40e_aqc_opc_get_rss_lut = 0x0B05,

	/* Async Events */		/* Async Events */
	i40e_aqc_opc_event_lan_overflow = 0x1001,		i40e_aqc_opc_event_lan_overflow = 0x1001,
	@@ -821,8 +825,12 @@ struct i40e_aqc_vsi_properties_data {
	I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT)		I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT)
	/* queueing option section */		/* queueing option section */
	u8 queueing_opt_flags;		u8 queueing_opt_flags;
			#define I40E_AQ_VSI_QUE_OPT_MULTICAST_UDP_ENA 0x04
			#define I40E_AQ_VSI_QUE_OPT_UNICAST_UDP_ENA 0x08
	#define I40E_AQ_VSI_QUE_OPT_TCP_ENA 0x10		#define I40E_AQ_VSI_QUE_OPT_TCP_ENA 0x10
	#define I40E_AQ_VSI_QUE_OPT_FCOE_ENA 0x20		#define I40E_AQ_VSI_QUE_OPT_FCOE_ENA 0x20
			#define I40E_AQ_VSI_QUE_OPT_RSS_LUT_PF 0x00
			#define I40E_AQ_VSI_QUE_OPT_RSS_LUT_VSI 0x40
	u8 queueing_opt_reserved[3];		u8 queueing_opt_reserved[3];
	/* scheduler section */		/* scheduler section */
	u8 up_enable_bits;		u8 up_enable_bits;
	@@ -2179,6 +2187,46 @@ struct i40e_aqc_del_udp_tunnel_completion {

	I40E_CHECK_CMD_LENGTH(i40e_aqc_del_udp_tunnel_completion);		I40E_CHECK_CMD_LENGTH(i40e_aqc_del_udp_tunnel_completion);

			struct i40e_aqc_get_set_rss_key {
			#define I40E_AQC_SET_RSS_KEY_VSI_VALID (0x1 << 15)
			#define I40E_AQC_SET_RSS_KEY_VSI_ID_SHIFT 0
			#define I40E_AQC_SET_RSS_KEY_VSI_ID_MASK (0x3FF << \
			I40E_AQC_SET_RSS_KEY_VSI_ID_SHIFT)
			__le16 vsi_id;
			u8 reserved[6];
			__le32 addr_high;
			__le32 addr_low;
			};

			I40E_CHECK_CMD_LENGTH(i40e_aqc_get_set_rss_key);

			struct i40e_aqc_get_set_rss_key_data {
			u8 standard_rss_key[0x28];
			u8 extended_hash_key[0xc];
			};

			I40E_CHECK_STRUCT_LEN(0x34, i40e_aqc_get_set_rss_key_data);

			struct i40e_aqc_get_set_rss_lut {
			#define I40E_AQC_SET_RSS_LUT_VSI_VALID (0x1 << 15)
			#define I40E_AQC_SET_RSS_LUT_VSI_ID_SHIFT 0
			#define I40E_AQC_SET_RSS_LUT_VSI_ID_MASK (0x3FF << \
			I40E_AQC_SET_RSS_LUT_VSI_ID_SHIFT)
			__le16 vsi_id;
			#define I40E_AQC_SET_RSS_LUT_TABLE_TYPE_SHIFT 0
			#define I40E_AQC_SET_RSS_LUT_TABLE_TYPE_MASK (0x1 << \
			I40E_AQC_SET_RSS_LUT_TABLE_TYPE_SHIFT)

			#define I40E_AQC_SET_RSS_LUT_TABLE_TYPE_VSI 0
			#define I40E_AQC_SET_RSS_LUT_TABLE_TYPE_PF 1
			__le16 flags;
			u8 reserved[4];
			__le32 addr_high;
			__le32 addr_low;
			};

			I40E_CHECK_CMD_LENGTH(i40e_aqc_get_set_rss_lut);

	/* tunnel key structure 0x0B10 */		/* tunnel key structure 0x0B10 */

	struct i40e_aqc_tunnel_key_structure {		struct i40e_aqc_tunnel_key_structure {