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Commit 1c7af42f authored by Olof Johansson's avatar Olof Johansson
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Merge branches 'depends/asoc-dma', 'depends/dma-of' and 'depends/tegra-clk' into next/cleanup 



Merging in external dependencies for the Tegra DMA and reset controller
refactoring from external trees.

Per Stephen Warren, the stability of these branches have been negotiated
with the relevant parties (Vinod/Mark/Mike)

* depends/asoc-dma:
  ASoC: dmaengine: fix deferred probe detection
  ASoC: dmaengine: support deferred probe for DMA channels
  dma: add channel request API that supports deferred probe
  ASoC: dmaengine: add custom DMA config to snd_dmaengine_pcm_config
  ASoC: don't leak on error in snd_dmaengine_pcm_register
  ASoC: restructure dmaengine_pcm_request_chan_of()
  ASoC: generic-dmaengine-pcm: Set BATCH flag when residue reporting is not supported
  ASoC: Add resource managed snd_dmaengine_pcm_register()

* depends/dma-of:
  dma: add dma_get_any_slave_channel(), for use in of_xlate()

* depends/tegra-clk: (42 commits)
  clk: tegra: fix __clk_lookup() return value checks
  clk: tegra: Do not print errors for clk_round_rate()
  clk: tegra: Initialize DSI low-power clocks
  clk: tegra: add FUSE clock device
  clk: tegra: Properly setup PWM clock on Tegra30
  clk: tegra: Initialize secondary gr3d clock on Tegra30
  clk: tegra114: Initialize clocks needed for HDMI
  clk: tegra124: add suspend/resume function for tegra_cpu_car_ops
  clk: tegra124: add wait_for_reset and disable_clock for tegra_cpu_car_ops
  clk: tegra124: Add support for Tegra124 clocks
  clk: tegra124: Add new peripheral clocks
  clk: tegra124: Add common clk IDs to clk-id.h
  clk: tegra: add TEGRA_PERIPH_NO_GATE
  clk: tegra: add locking to periph clks
  clk: tegra: Add periph regs bank X
  clk: tegra: Add support for PLLSS
  clk: tegra: move tegra20 to common infra
  clk: tegra: move tegra30 to common infra
  clk: tegra: introduce common gen4 super clock
  clk: tegra: move PMC, fixed clocks to common files
  ...

Signed-off-by: default avatarOlof Johansson <olof@lixom.net>
parents 509633c8 e9036c2a 8010dad5 62ce7cd6

Documentation/devicetree/bindings/clock/nvidia,tegra124-car.txt

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+59 −0
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NVIDIA Tegra124 Clock And Reset Controller



This binding uses the common clock binding:

Documentation/devicetree/bindings/clock/clock-bindings.txt



The CAR (Clock And Reset) Controller on Tegra is the HW module responsible

for muxing and gating Tegra's clocks, and setting their rates.



Required properties :

- compatible : Should be "nvidia,tegra124-car"

- reg : Should contain CAR registers location and length

- clocks : Should contain phandle and clock specifiers for two clocks:

  the 32 KHz "32k_in", and the board-specific oscillator "osc".

- #clock-cells : Should be 1.

  In clock consumers, this cell represents the clock ID exposed by the

  CAR. The assignments may be found in header file

  <dt-bindings/clock/tegra124-car.h>.



Example SoC include file:



/ {

	tegra_car: clock {

		compatible = "nvidia,tegra124-car";

		reg = <0x60006000 0x1000>;

		#clock-cells = <1>;

	};



	usb@c5004000 {

		clocks = <&tegra_car TEGRA124_CLK_USB2>;

	};

};



Example board file:



/ {

	clocks {

		compatible = "simple-bus";

		#address-cells = <1>;

		#size-cells = <0>;



		osc: clock@0 {

			compatible = "fixed-clock";

			reg = <0>;

			#clock-cells = <0>;

			clock-frequency = <112400000>;

		};



		clk_32k: clock@1 {

			compatible = "fixed-clock";

			reg = <1>;

			#clock-cells = <0>;

			clock-frequency = <32768>;

		};

	};



	&tegra_car {

		clocks = <&clk_32k> <&osc>;

	};

};

drivers/clk/tegra/Makefile

+6 −1
Original line number Diff line number Diff line
@@ -6,7 +6,12 @@ obj-y += clk-periph-gate.o 
obj-y					+= clk-pll.o

obj-y					+= clk-pll-out.o

obj-y					+= clk-super.o



obj-y					+= clk-tegra-audio.o

obj-y					+= clk-tegra-periph.o

obj-y					+= clk-tegra-pmc.o

obj-y					+= clk-tegra-fixed.o

obj-y					+= clk-tegra-super-gen4.o

obj-$(CONFIG_ARCH_TEGRA_2x_SOC)         += clk-tegra20.o

obj-$(CONFIG_ARCH_TEGRA_3x_SOC)         += clk-tegra30.o

obj-$(CONFIG_ARCH_TEGRA_114_SOC)	+= clk-tegra114.o

obj-$(CONFIG_ARCH_TEGRA_124_SOC)	+= clk-tegra124.o

drivers/clk/tegra/clk-id.h

0 → 100644
+235 −0
Original line number Diff line number Diff line 
/*

 * This header provides IDs for clocks common between several Tegra SoCs

 */

#ifndef _TEGRA_CLK_ID_H

#define _TEGRA_CLK_ID_H



enum clk_id {

	tegra_clk_actmon,

	tegra_clk_adx,

	tegra_clk_adx1,

	tegra_clk_afi,

	tegra_clk_amx,

	tegra_clk_amx1,

	tegra_clk_apbdma,

	tegra_clk_apbif,

	tegra_clk_audio0,

	tegra_clk_audio0_2x,

	tegra_clk_audio0_mux,

	tegra_clk_audio1,

	tegra_clk_audio1_2x,

	tegra_clk_audio1_mux,

	tegra_clk_audio2,

	tegra_clk_audio2_2x,

	tegra_clk_audio2_mux,

	tegra_clk_audio3,

	tegra_clk_audio3_2x,

	tegra_clk_audio3_mux,

	tegra_clk_audio4,

	tegra_clk_audio4_2x,

	tegra_clk_audio4_mux,

	tegra_clk_blink,

	tegra_clk_bsea,

	tegra_clk_bsev,

	tegra_clk_cclk_g,

	tegra_clk_cclk_lp,

	tegra_clk_cilab,

	tegra_clk_cilcd,

	tegra_clk_cile,

	tegra_clk_clk_32k,

	tegra_clk_clk72Mhz,

	tegra_clk_clk_m,

	tegra_clk_clk_m_div2,

	tegra_clk_clk_m_div4,

	tegra_clk_clk_out_1,

	tegra_clk_clk_out_1_mux,

	tegra_clk_clk_out_2,

	tegra_clk_clk_out_2_mux,

	tegra_clk_clk_out_3,

	tegra_clk_clk_out_3_mux,

	tegra_clk_cml0,

	tegra_clk_cml1,

	tegra_clk_csi,

	tegra_clk_csite,

	tegra_clk_csus,

	tegra_clk_cve,

	tegra_clk_dam0,

	tegra_clk_dam1,

	tegra_clk_dam2,

	tegra_clk_d_audio,

	tegra_clk_dds,

	tegra_clk_dfll_ref,

	tegra_clk_dfll_soc,

	tegra_clk_disp1,

	tegra_clk_disp2,

	tegra_clk_dp2,

	tegra_clk_dpaux,

	tegra_clk_dsia,

	tegra_clk_dsialp,

	tegra_clk_dsia_mux,

	tegra_clk_dsib,

	tegra_clk_dsiblp,

	tegra_clk_dsib_mux,

	tegra_clk_dtv,

	tegra_clk_emc,

	tegra_clk_entropy,

	tegra_clk_epp,

	tegra_clk_epp_8,

	tegra_clk_extern1,

	tegra_clk_extern2,

	tegra_clk_extern3,

	tegra_clk_fuse,

	tegra_clk_fuse_burn,

	tegra_clk_gpu,

	tegra_clk_gr2d,

	tegra_clk_gr2d_8,

	tegra_clk_gr3d,

	tegra_clk_gr3d_8,

	tegra_clk_hclk,

	tegra_clk_hda,

	tegra_clk_hda2codec_2x,

	tegra_clk_hda2hdmi,

	tegra_clk_hdmi,

	tegra_clk_hdmi_audio,

	tegra_clk_host1x,

	tegra_clk_host1x_8,

	tegra_clk_i2c1,

	tegra_clk_i2c2,

	tegra_clk_i2c3,

	tegra_clk_i2c4,

	tegra_clk_i2c5,

	tegra_clk_i2c6,

	tegra_clk_i2cslow,

	tegra_clk_i2s0,

	tegra_clk_i2s0_sync,

	tegra_clk_i2s1,

	tegra_clk_i2s1_sync,

	tegra_clk_i2s2,

	tegra_clk_i2s2_sync,

	tegra_clk_i2s3,

	tegra_clk_i2s3_sync,

	tegra_clk_i2s4,

	tegra_clk_i2s4_sync,

	tegra_clk_isp,

	tegra_clk_isp_8,

	tegra_clk_ispb,

	tegra_clk_kbc,

	tegra_clk_kfuse,

	tegra_clk_la,

	tegra_clk_mipi,

	tegra_clk_mipi_cal,

	tegra_clk_mpe,

	tegra_clk_mselect,

	tegra_clk_msenc,

	tegra_clk_ndflash,

	tegra_clk_ndflash_8,

	tegra_clk_ndspeed,

	tegra_clk_ndspeed_8,

	tegra_clk_nor,

	tegra_clk_owr,

	tegra_clk_pcie,

	tegra_clk_pclk,

	tegra_clk_pll_a,

	tegra_clk_pll_a_out0,

	tegra_clk_pll_c,

	tegra_clk_pll_c2,

	tegra_clk_pll_c3,

	tegra_clk_pll_c4,

	tegra_clk_pll_c_out1,

	tegra_clk_pll_d,

	tegra_clk_pll_d2,

	tegra_clk_pll_d2_out0,

	tegra_clk_pll_d_out0,

	tegra_clk_pll_dp,

	tegra_clk_pll_e_out0,

	tegra_clk_pll_m,

	tegra_clk_pll_m_out1,

	tegra_clk_pll_p,

	tegra_clk_pll_p_out1,

	tegra_clk_pll_p_out2,

	tegra_clk_pll_p_out2_int,

	tegra_clk_pll_p_out3,

	tegra_clk_pll_p_out4,

	tegra_clk_pll_p_out5,

	tegra_clk_pll_ref,

	tegra_clk_pll_re_out,

	tegra_clk_pll_re_vco,

	tegra_clk_pll_u,

	tegra_clk_pll_u_12m,

	tegra_clk_pll_u_480m,

	tegra_clk_pll_u_48m,

	tegra_clk_pll_u_60m,

	tegra_clk_pll_x,

	tegra_clk_pll_x_out0,

	tegra_clk_pwm,

	tegra_clk_rtc,

	tegra_clk_sata,

	tegra_clk_sata_cold,

	tegra_clk_sata_oob,

	tegra_clk_sbc1,

	tegra_clk_sbc1_8,

	tegra_clk_sbc2,

	tegra_clk_sbc2_8,

	tegra_clk_sbc3,

	tegra_clk_sbc3_8,

	tegra_clk_sbc4,

	tegra_clk_sbc4_8,

	tegra_clk_sbc5,

	tegra_clk_sbc5_8,

	tegra_clk_sbc6,

	tegra_clk_sbc6_8,

	tegra_clk_sclk,

	tegra_clk_sdmmc1,

	tegra_clk_sdmmc2,

	tegra_clk_sdmmc3,

	tegra_clk_sdmmc4,

	tegra_clk_se,

	tegra_clk_soc_therm,

	tegra_clk_sor0,

	tegra_clk_sor0_lvds,

	tegra_clk_spdif,

	tegra_clk_spdif_2x,

	tegra_clk_spdif_in,

	tegra_clk_spdif_in_sync,

	tegra_clk_spdif_mux,

	tegra_clk_spdif_out,

	tegra_clk_timer,

	tegra_clk_trace,

	tegra_clk_tsec,

	tegra_clk_tsensor,

	tegra_clk_tvdac,

	tegra_clk_tvo,

	tegra_clk_uarta,

	tegra_clk_uartb,

	tegra_clk_uartc,

	tegra_clk_uartd,

	tegra_clk_uarte,

	tegra_clk_usb2,

	tegra_clk_usb3,

	tegra_clk_usbd,

	tegra_clk_vcp,

	tegra_clk_vde,

	tegra_clk_vde_8,

	tegra_clk_vfir,

	tegra_clk_vi,

	tegra_clk_vi_8,

	tegra_clk_vi_9,

	tegra_clk_vic03,

	tegra_clk_vim2_clk,

	tegra_clk_vimclk_sync,

	tegra_clk_vi_sensor,

	tegra_clk_vi_sensor2,

	tegra_clk_vi_sensor_8,

	tegra_clk_xusb_dev,

	tegra_clk_xusb_dev_src,

	tegra_clk_xusb_falcon_src,

	tegra_clk_xusb_fs_src,

	tegra_clk_xusb_host,

	tegra_clk_xusb_host_src,

	tegra_clk_xusb_hs_src,

	tegra_clk_xusb_ss,

	tegra_clk_xusb_ss_src,

	tegra_clk_max,

};



#endif	/* _TEGRA_CLK_ID_H */

drivers/clk/tegra/clk-periph-gate.c

+6 −2
Original line number Diff line number Diff line
@@ -151,12 +151,16 @@ const struct clk_ops tegra_clk_periph_gate_ops = { 


struct clk *tegra_clk_register_periph_gate(const char *name,

		const char *parent_name, u8 gate_flags, void __iomem *clk_base,

		unsigned long flags, int clk_num,

		struct tegra_clk_periph_regs *pregs, int *enable_refcnt)

		unsigned long flags, int clk_num, int *enable_refcnt)

{

	struct tegra_clk_periph_gate *gate;

	struct clk *clk;

	struct clk_init_data init;

	struct tegra_clk_periph_regs *pregs;



	pregs = get_reg_bank(clk_num);

	if (!pregs)

		return ERR_PTR(-EINVAL);



	gate = kzalloc(sizeof(*gate), GFP_KERNEL);

	if (!gate) {

drivers/clk/tegra/clk-periph.c

+28 −4
Original line number Diff line number Diff line
@@ -170,27 +170,50 @@ const struct clk_ops tegra_clk_periph_nodiv_ops = { 
	.disable = clk_periph_disable,

};



const struct clk_ops tegra_clk_periph_no_gate_ops = {

	.get_parent = clk_periph_get_parent,

	.set_parent = clk_periph_set_parent,

	.recalc_rate = clk_periph_recalc_rate,

	.round_rate = clk_periph_round_rate,

	.set_rate = clk_periph_set_rate,

};



static struct clk *_tegra_clk_register_periph(const char *name,

			const char **parent_names, int num_parents,

			struct tegra_clk_periph *periph,

			void __iomem *clk_base, u32 offset, bool div,

			void __iomem *clk_base, u32 offset,

			unsigned long flags)

{

	struct clk *clk;

	struct clk_init_data init;

	struct tegra_clk_periph_regs *bank;

	bool div = !(periph->gate.flags & TEGRA_PERIPH_NO_DIV);



	if (periph->gate.flags & TEGRA_PERIPH_NO_DIV) {

		flags |= CLK_SET_RATE_PARENT;

		init.ops = &tegra_clk_periph_nodiv_ops;

	} else if (periph->gate.flags & TEGRA_PERIPH_NO_GATE)

		init.ops = &tegra_clk_periph_no_gate_ops;

	else

		init.ops = &tegra_clk_periph_ops;



	init.name = name;

	init.ops = div ? &tegra_clk_periph_ops : &tegra_clk_periph_nodiv_ops;

	init.flags = flags;

	init.parent_names = parent_names;

	init.num_parents = num_parents;



	bank = get_reg_bank(periph->gate.clk_num);

	if (!bank)

		return ERR_PTR(-EINVAL);



	/* Data in .init is copied by clk_register(), so stack variable OK */

	periph->hw.init = &init;

	periph->magic = TEGRA_CLK_PERIPH_MAGIC;

	periph->mux.reg = clk_base + offset;

	periph->divider.reg = div ? (clk_base + offset) : NULL;

	periph->gate.clk_base = clk_base;

	periph->gate.regs = bank;

	periph->gate.enable_refcnt = periph_clk_enb_refcnt;



	clk = clk_register(NULL, &periph->hw);

	if (IS_ERR(clk))
@@ -209,7 +232,7 @@ struct clk *tegra_clk_register_periph(const char *name, 
		u32 offset, unsigned long flags)

{

	return _tegra_clk_register_periph(name, parent_names, num_parents,

			periph, clk_base, offset, true, flags);

			periph, clk_base, offset, flags);

}



struct clk *tegra_clk_register_periph_nodiv(const char *name,
@@ -217,6 +240,7 @@ struct clk *tegra_clk_register_periph_nodiv(const char *name, 
		struct tegra_clk_periph *periph, void __iomem *clk_base,

		u32 offset)

{

	periph->gate.flags |= TEGRA_PERIPH_NO_DIV;

	return _tegra_clk_register_periph(name, parent_names, num_parents,

			periph, clk_base, offset, false, CLK_SET_RATE_PARENT);

			periph, clk_base, offset, CLK_SET_RATE_PARENT);

}