Donate to e Foundation | Murena handsets with /e/OS | Own a part of Murena! Learn more

Commit 18aecc2b authored by Chris Metcalf's avatar Chris Metcalf
Browse files

arch/tile: finish enabling support for TILE-Gx 64-bit chip 



This support was partially present in the existing code (look for
"__tilegx__" ifdefs) but with this change you can build a working
kernel using the TILE-Gx toolchain and ARCH=tilegx.

Most of these files are new, generally adding a foo_64.c file
where previously there was just a foo_32.c file.

The ARCH=tilegx directive redirects to arch/tile, not arch/tilegx,
using the existing SRCARCH mechanism in the top-level Makefile.

Changes to existing files:

- <asm/bitops.h> and <asm/bitops_32.h> changed to factor the
  include of <asm-generic/bitops/non-atomic.h> in the common header.

- <asm/compat.h> and arch/tile/kernel/compat.c changed to remove
  the "const" markers I had put on compat_sys_execve() when trying
  to match some recent similar changes to the non-compat execve.
  It turns out the compat version wasn't "upgraded" to use const.

- <asm/opcode-tile_64.h> and <asm/opcode_constants_64.h> were
  previously included accidentally, with the 32-bit contents.  Now
  they have the proper 64-bit contents.

Finally, I had to hack the existing hacky drivers/input/input-compat.h
to add yet another "#ifdef" for INPUT_COMPAT_TEST (same as x86_64).

Signed-off-by: default avatarChris Metcalf <cmetcalf@tilera.com>
Acked-by: Dmitry Torokhov <dmitry.torokhov@gmail.com> [drivers/input]
parent be84cb43

Makefile

+5 −0
Original line number Diff line number Diff line
@@ -220,6 +220,11 @@ ifeq ($(ARCH),sh64) 
       SRCARCH := sh

endif



# Additional ARCH settings for tile

ifeq ($(ARCH),tilegx)

       SRCARCH := tile

endif



# Where to locate arch specific headers

hdr-arch  := $(SRCARCH)

arch/tile/configs/tilegx_defconfig

0 → 100644
+1776 −0

File added.

Preview size limit exceeded, changes collapsed.

arch/tile/include/arch/chip_tilegx.h

0 → 100644
+258 −0
Original line number Diff line number Diff line 
/*

 * Copyright 2011 Tilera Corporation. All Rights Reserved.

 *

 *   This program is free software; you can redistribute it and/or

 *   modify it under the terms of the GNU General Public License

 *   as published by the Free Software Foundation, version 2.

 *

 *   This program is distributed in the hope that it will be useful, but

 *   WITHOUT ANY WARRANTY; without even the implied warranty of

 *   MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or

 *   NON INFRINGEMENT.  See the GNU General Public License for

 *   more details.

 */



/*

 * @file

 * Global header file.

 * This header file specifies defines for TILE-Gx.

 */



#ifndef __ARCH_CHIP_H__

#define __ARCH_CHIP_H__



/** Specify chip version.

 * When possible, prefer the CHIP_xxx symbols below for future-proofing.

 * This is intended for cross-compiling; native compilation should

 * use the predefined __tile_chip__ symbol.

 */

#define TILE_CHIP 10



/** Specify chip revision.

 * This provides for the case of a respin of a particular chip type;

 * the normal value for this symbol is "0".

 * This is intended for cross-compiling; native compilation should

 * use the predefined __tile_chip_rev__ symbol.

 */

#define TILE_CHIP_REV 0



/** The name of this architecture. */

#define CHIP_ARCH_NAME "tilegx"



/** The ELF e_machine type for binaries for this chip. */

#define CHIP_ELF_TYPE() EM_TILEGX



/** The alternate ELF e_machine type for binaries for this chip. */

#define CHIP_COMPAT_ELF_TYPE() 0x2597



/** What is the native word size of the machine? */

#define CHIP_WORD_SIZE() 64



/** How many bits of a virtual address are used. Extra bits must be

 * the sign extension of the low bits.

 */

#define CHIP_VA_WIDTH() 42



/** How many bits are in a physical address? */

#define CHIP_PA_WIDTH() 40



/** Size of the L2 cache, in bytes. */

#define CHIP_L2_CACHE_SIZE() 262144



/** Log size of an L2 cache line in bytes. */

#define CHIP_L2_LOG_LINE_SIZE() 6



/** Size of an L2 cache line, in bytes. */

#define CHIP_L2_LINE_SIZE() (1 << CHIP_L2_LOG_LINE_SIZE())



/** Associativity of the L2 cache. */

#define CHIP_L2_ASSOC() 8



/** Size of the L1 data cache, in bytes. */

#define CHIP_L1D_CACHE_SIZE() 32768



/** Log size of an L1 data cache line in bytes. */

#define CHIP_L1D_LOG_LINE_SIZE() 6



/** Size of an L1 data cache line, in bytes. */

#define CHIP_L1D_LINE_SIZE() (1 << CHIP_L1D_LOG_LINE_SIZE())



/** Associativity of the L1 data cache. */

#define CHIP_L1D_ASSOC() 2



/** Size of the L1 instruction cache, in bytes. */

#define CHIP_L1I_CACHE_SIZE() 32768



/** Log size of an L1 instruction cache line in bytes. */

#define CHIP_L1I_LOG_LINE_SIZE() 6



/** Size of an L1 instruction cache line, in bytes. */

#define CHIP_L1I_LINE_SIZE() (1 << CHIP_L1I_LOG_LINE_SIZE())



/** Associativity of the L1 instruction cache. */

#define CHIP_L1I_ASSOC() 2



/** Stride with which flush instructions must be issued. */

#define CHIP_FLUSH_STRIDE() CHIP_L2_LINE_SIZE()



/** Stride with which inv instructions must be issued. */

#define CHIP_INV_STRIDE() CHIP_L2_LINE_SIZE()



/** Stride with which finv instructions must be issued. */

#define CHIP_FINV_STRIDE() CHIP_L2_LINE_SIZE()



/** Can the local cache coherently cache data that is homed elsewhere? */

#define CHIP_HAS_COHERENT_LOCAL_CACHE() 1



/** How many simultaneous outstanding victims can the L2 cache have? */

#define CHIP_MAX_OUTSTANDING_VICTIMS() 128



/** Does the TLB support the NC and NOALLOC bits? */

#define CHIP_HAS_NC_AND_NOALLOC_BITS() 1



/** Does the chip support hash-for-home caching? */

#define CHIP_HAS_CBOX_HOME_MAP() 1



/** Number of entries in the chip's home map tables. */

#define CHIP_CBOX_HOME_MAP_SIZE() 128



/** Do uncacheable requests miss in the cache regardless of whether

 * there is matching data? */

#define CHIP_HAS_ENFORCED_UNCACHEABLE_REQUESTS() 1



/** Does the mf instruction wait for victims? */

#define CHIP_HAS_MF_WAITS_FOR_VICTIMS() 0



/** Does the chip have an "inv" instruction that doesn't also flush? */

#define CHIP_HAS_INV() 1



/** Does the chip have a "wh64" instruction? */

#define CHIP_HAS_WH64() 1



/** Does this chip have a 'dword_align' instruction? */

#define CHIP_HAS_DWORD_ALIGN() 0



/** Number of performance counters. */

#define CHIP_PERFORMANCE_COUNTERS() 4



/** Does this chip have auxiliary performance counters? */

#define CHIP_HAS_AUX_PERF_COUNTERS() 1



/** Is the CBOX_MSR1 SPR supported? */

#define CHIP_HAS_CBOX_MSR1() 0



/** Is the TILE_RTF_HWM SPR supported? */

#define CHIP_HAS_TILE_RTF_HWM() 1



/** Is the TILE_WRITE_PENDING SPR supported? */

#define CHIP_HAS_TILE_WRITE_PENDING() 0



/** Is the PROC_STATUS SPR supported? */

#define CHIP_HAS_PROC_STATUS_SPR() 1



/** Is the DSTREAM_PF SPR supported? */

#define CHIP_HAS_DSTREAM_PF() 1



/** Log of the number of mshims we have. */

#define CHIP_LOG_NUM_MSHIMS() 2



/** Are the bases of the interrupt vector areas fixed? */

#define CHIP_HAS_FIXED_INTVEC_BASE() 0



/** Are the interrupt masks split up into 2 SPRs? */

#define CHIP_HAS_SPLIT_INTR_MASK() 0



/** Is the cycle count split up into 2 SPRs? */

#define CHIP_HAS_SPLIT_CYCLE() 0



/** Does the chip have a static network? */

#define CHIP_HAS_SN() 0



/** Does the chip have a static network processor? */

#define CHIP_HAS_SN_PROC() 0



/** Size of the L1 static network processor instruction cache, in bytes. */

/* #define CHIP_L1SNI_CACHE_SIZE() -- does not apply to chip 10 */



/** Does the chip have DMA support in each tile? */

#define CHIP_HAS_TILE_DMA() 0



/** Does the chip have the second revision of the directly accessible

 *  dynamic networks?  This encapsulates a number of characteristics,

 *  including the absence of the catch-all, the absence of inline message

 *  tags, the absence of support for network context-switching, and so on.

 */

#define CHIP_HAS_REV1_XDN() 1



/** Does the chip have cmpexch and similar (fetchadd, exch, etc.)? */

#define CHIP_HAS_CMPEXCH() 1



/** Does the chip have memory-mapped I/O support? */

#define CHIP_HAS_MMIO() 1



/** Does the chip have post-completion interrupts? */

#define CHIP_HAS_POST_COMPLETION_INTERRUPTS() 1



/** Does the chip have native single step support? */

#define CHIP_HAS_SINGLE_STEP() 1



#ifndef __OPEN_SOURCE__  /* features only relevant to hypervisor-level code */



/** How many entries are present in the instruction TLB? */

#define CHIP_ITLB_ENTRIES() 16



/** How many entries are present in the data TLB? */

#define CHIP_DTLB_ENTRIES() 32



/** How many MAF entries does the XAUI shim have? */

#define CHIP_XAUI_MAF_ENTRIES() 32



/** Does the memory shim have a source-id table? */

#define CHIP_HAS_MSHIM_SRCID_TABLE() 0



/** Does the L1 instruction cache clear on reset? */

#define CHIP_HAS_L1I_CLEAR_ON_RESET() 1



/** Does the chip come out of reset with valid coordinates on all tiles?

 * Note that if defined, this also implies that the upper left is 1,1.

 */

#define CHIP_HAS_VALID_TILE_COORD_RESET() 1



/** Does the chip have unified packet formats? */

#define CHIP_HAS_UNIFIED_PACKET_FORMATS() 1



/** Does the chip support write reordering? */

#define CHIP_HAS_WRITE_REORDERING() 1



/** Does the chip support Y-X routing as well as X-Y? */

#define CHIP_HAS_Y_X_ROUTING() 1



/** Is INTCTRL_3 managed with the correct MPL? */

#define CHIP_HAS_INTCTRL_3_STATUS_FIX() 1



/** Is it possible to configure the chip to be big-endian? */

#define CHIP_HAS_BIG_ENDIAN_CONFIG() 1



/** Is the CACHE_RED_WAY_OVERRIDDEN SPR supported? */

#define CHIP_HAS_CACHE_RED_WAY_OVERRIDDEN() 0



/** Is the DIAG_TRACE_WAY SPR supported? */

#define CHIP_HAS_DIAG_TRACE_WAY() 0



/** Is the MEM_STRIPE_CONFIG SPR supported? */

#define CHIP_HAS_MEM_STRIPE_CONFIG() 1



/** Are the TLB_PERF SPRs supported? */

#define CHIP_HAS_TLB_PERF() 1



/** Is the VDN_SNOOP_SHIM_CTL SPR supported? */

#define CHIP_HAS_VDN_SNOOP_SHIM_CTL() 0



/** Does the chip support rev1 DMA packets? */

#define CHIP_HAS_REV1_DMA_PACKETS() 1



/** Does the chip have an IPI shim? */

#define CHIP_HAS_IPI() 1



#endif /* !__OPEN_SOURCE__ */

#endif /* __ARCH_CHIP_H__ */

arch/tile/include/arch/interrupts_64.h

0 → 100644
+276 −0
Original line number Diff line number Diff line 
/*

 * Copyright 2011 Tilera Corporation. All Rights Reserved.

 *

 *   This program is free software; you can redistribute it and/or

 *   modify it under the terms of the GNU General Public License

 *   as published by the Free Software Foundation, version 2.

 *

 *   This program is distributed in the hope that it will be useful, but

 *   WITHOUT ANY WARRANTY; without even the implied warranty of

 *   MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or

 *   NON INFRINGEMENT.  See the GNU General Public License for

 *   more details.

 */



#ifndef __ARCH_INTERRUPTS_H__

#define __ARCH_INTERRUPTS_H__



/** Mask for an interrupt. */

#ifdef __ASSEMBLER__

/* Note: must handle breaking interrupts into high and low words manually. */

#define INT_MASK(intno) (1 << (intno))

#else

#define INT_MASK(intno) (1ULL << (intno))

#endif





/** Where a given interrupt executes */

#define INTERRUPT_VECTOR(i, pl) (0xFC000000 + ((pl) << 24) + ((i) << 8))



/** Where to store a vector for a given interrupt. */

#define USER_INTERRUPT_VECTOR(i) INTERRUPT_VECTOR(i, 0)



/** The base address of user-level interrupts. */

#define USER_INTERRUPT_VECTOR_BASE INTERRUPT_VECTOR(0, 0)





/** Additional synthetic interrupt. */

#define INT_BREAKPOINT (63)



#define INT_MEM_ERROR    0

#define INT_SINGLE_STEP_3    1

#define INT_SINGLE_STEP_2    2

#define INT_SINGLE_STEP_1    3

#define INT_SINGLE_STEP_0    4

#define INT_IDN_COMPLETE    5

#define INT_UDN_COMPLETE    6

#define INT_ITLB_MISS    7

#define INT_ILL    8

#define INT_GPV    9

#define INT_IDN_ACCESS   10

#define INT_UDN_ACCESS   11

#define INT_SWINT_3   12

#define INT_SWINT_2   13

#define INT_SWINT_1   14

#define INT_SWINT_0   15

#define INT_ILL_TRANS   16

#define INT_UNALIGN_DATA   17

#define INT_DTLB_MISS   18

#define INT_DTLB_ACCESS   19

#define INT_IDN_FIREWALL   20

#define INT_UDN_FIREWALL   21

#define INT_TILE_TIMER   22

#define INT_AUX_TILE_TIMER   23

#define INT_IDN_TIMER   24

#define INT_UDN_TIMER   25

#define INT_IDN_AVAIL   26

#define INT_UDN_AVAIL   27

#define INT_IPI_3   28

#define INT_IPI_2   29

#define INT_IPI_1   30

#define INT_IPI_0   31

#define INT_PERF_COUNT   32

#define INT_AUX_PERF_COUNT   33

#define INT_INTCTRL_3   34

#define INT_INTCTRL_2   35

#define INT_INTCTRL_1   36

#define INT_INTCTRL_0   37

#define INT_BOOT_ACCESS   38

#define INT_WORLD_ACCESS   39

#define INT_I_ASID   40

#define INT_D_ASID   41

#define INT_DOUBLE_FAULT   42



#define NUM_INTERRUPTS 43



#ifndef __ASSEMBLER__

#define QUEUED_INTERRUPTS ( \

    INT_MASK(INT_MEM_ERROR) | \

    INT_MASK(INT_IDN_COMPLETE) | \

    INT_MASK(INT_UDN_COMPLETE) | \

    INT_MASK(INT_IDN_FIREWALL) | \

    INT_MASK(INT_UDN_FIREWALL) | \

    INT_MASK(INT_TILE_TIMER) | \

    INT_MASK(INT_AUX_TILE_TIMER) | \

    INT_MASK(INT_IDN_TIMER) | \

    INT_MASK(INT_UDN_TIMER) | \

    INT_MASK(INT_IDN_AVAIL) | \

    INT_MASK(INT_UDN_AVAIL) | \

    INT_MASK(INT_IPI_3) | \

    INT_MASK(INT_IPI_2) | \

    INT_MASK(INT_IPI_1) | \

    INT_MASK(INT_IPI_0) | \

    INT_MASK(INT_PERF_COUNT) | \

    INT_MASK(INT_AUX_PERF_COUNT) | \

    INT_MASK(INT_INTCTRL_3) | \

    INT_MASK(INT_INTCTRL_2) | \

    INT_MASK(INT_INTCTRL_1) | \

    INT_MASK(INT_INTCTRL_0) | \

    INT_MASK(INT_BOOT_ACCESS) | \

    INT_MASK(INT_WORLD_ACCESS) | \

    INT_MASK(INT_I_ASID) | \

    INT_MASK(INT_D_ASID) | \

    INT_MASK(INT_DOUBLE_FAULT) | \

    0)

#define NONQUEUED_INTERRUPTS ( \

    INT_MASK(INT_SINGLE_STEP_3) | \

    INT_MASK(INT_SINGLE_STEP_2) | \

    INT_MASK(INT_SINGLE_STEP_1) | \

    INT_MASK(INT_SINGLE_STEP_0) | \

    INT_MASK(INT_ITLB_MISS) | \

    INT_MASK(INT_ILL) | \

    INT_MASK(INT_GPV) | \

    INT_MASK(INT_IDN_ACCESS) | \

    INT_MASK(INT_UDN_ACCESS) | \

    INT_MASK(INT_SWINT_3) | \

    INT_MASK(INT_SWINT_2) | \

    INT_MASK(INT_SWINT_1) | \

    INT_MASK(INT_SWINT_0) | \

    INT_MASK(INT_ILL_TRANS) | \

    INT_MASK(INT_UNALIGN_DATA) | \

    INT_MASK(INT_DTLB_MISS) | \

    INT_MASK(INT_DTLB_ACCESS) | \

    0)

#define CRITICAL_MASKED_INTERRUPTS ( \

    INT_MASK(INT_MEM_ERROR) | \

    INT_MASK(INT_SINGLE_STEP_3) | \

    INT_MASK(INT_SINGLE_STEP_2) | \

    INT_MASK(INT_SINGLE_STEP_1) | \

    INT_MASK(INT_SINGLE_STEP_0) | \

    INT_MASK(INT_IDN_COMPLETE) | \

    INT_MASK(INT_UDN_COMPLETE) | \

    INT_MASK(INT_IDN_FIREWALL) | \

    INT_MASK(INT_UDN_FIREWALL) | \

    INT_MASK(INT_TILE_TIMER) | \

    INT_MASK(INT_AUX_TILE_TIMER) | \

    INT_MASK(INT_IDN_TIMER) | \

    INT_MASK(INT_UDN_TIMER) | \

    INT_MASK(INT_IDN_AVAIL) | \

    INT_MASK(INT_UDN_AVAIL) | \

    INT_MASK(INT_IPI_3) | \

    INT_MASK(INT_IPI_2) | \

    INT_MASK(INT_IPI_1) | \

    INT_MASK(INT_IPI_0) | \

    INT_MASK(INT_PERF_COUNT) | \

    INT_MASK(INT_AUX_PERF_COUNT) | \

    INT_MASK(INT_INTCTRL_3) | \

    INT_MASK(INT_INTCTRL_2) | \

    INT_MASK(INT_INTCTRL_1) | \

    INT_MASK(INT_INTCTRL_0) | \

    0)

#define CRITICAL_UNMASKED_INTERRUPTS ( \

    INT_MASK(INT_ITLB_MISS) | \

    INT_MASK(INT_ILL) | \

    INT_MASK(INT_GPV) | \

    INT_MASK(INT_IDN_ACCESS) | \

    INT_MASK(INT_UDN_ACCESS) | \

    INT_MASK(INT_SWINT_3) | \

    INT_MASK(INT_SWINT_2) | \

    INT_MASK(INT_SWINT_1) | \

    INT_MASK(INT_SWINT_0) | \

    INT_MASK(INT_ILL_TRANS) | \

    INT_MASK(INT_UNALIGN_DATA) | \

    INT_MASK(INT_DTLB_MISS) | \

    INT_MASK(INT_DTLB_ACCESS) | \

    INT_MASK(INT_BOOT_ACCESS) | \

    INT_MASK(INT_WORLD_ACCESS) | \

    INT_MASK(INT_I_ASID) | \

    INT_MASK(INT_D_ASID) | \

    INT_MASK(INT_DOUBLE_FAULT) | \

    0)

#define MASKABLE_INTERRUPTS ( \

    INT_MASK(INT_MEM_ERROR) | \

    INT_MASK(INT_SINGLE_STEP_3) | \

    INT_MASK(INT_SINGLE_STEP_2) | \

    INT_MASK(INT_SINGLE_STEP_1) | \

    INT_MASK(INT_SINGLE_STEP_0) | \

    INT_MASK(INT_IDN_COMPLETE) | \

    INT_MASK(INT_UDN_COMPLETE) | \

    INT_MASK(INT_IDN_FIREWALL) | \

    INT_MASK(INT_UDN_FIREWALL) | \

    INT_MASK(INT_TILE_TIMER) | \

    INT_MASK(INT_AUX_TILE_TIMER) | \

    INT_MASK(INT_IDN_TIMER) | \

    INT_MASK(INT_UDN_TIMER) | \

    INT_MASK(INT_IDN_AVAIL) | \

    INT_MASK(INT_UDN_AVAIL) | \

    INT_MASK(INT_IPI_3) | \

    INT_MASK(INT_IPI_2) | \

    INT_MASK(INT_IPI_1) | \

    INT_MASK(INT_IPI_0) | \

    INT_MASK(INT_PERF_COUNT) | \

    INT_MASK(INT_AUX_PERF_COUNT) | \

    INT_MASK(INT_INTCTRL_3) | \

    INT_MASK(INT_INTCTRL_2) | \

    INT_MASK(INT_INTCTRL_1) | \

    INT_MASK(INT_INTCTRL_0) | \

    0)

#define UNMASKABLE_INTERRUPTS ( \

    INT_MASK(INT_ITLB_MISS) | \

    INT_MASK(INT_ILL) | \

    INT_MASK(INT_GPV) | \

    INT_MASK(INT_IDN_ACCESS) | \

    INT_MASK(INT_UDN_ACCESS) | \

    INT_MASK(INT_SWINT_3) | \

    INT_MASK(INT_SWINT_2) | \

    INT_MASK(INT_SWINT_1) | \

    INT_MASK(INT_SWINT_0) | \

    INT_MASK(INT_ILL_TRANS) | \

    INT_MASK(INT_UNALIGN_DATA) | \

    INT_MASK(INT_DTLB_MISS) | \

    INT_MASK(INT_DTLB_ACCESS) | \

    INT_MASK(INT_BOOT_ACCESS) | \

    INT_MASK(INT_WORLD_ACCESS) | \

    INT_MASK(INT_I_ASID) | \

    INT_MASK(INT_D_ASID) | \

    INT_MASK(INT_DOUBLE_FAULT) | \

    0)

#define SYNC_INTERRUPTS ( \

    INT_MASK(INT_SINGLE_STEP_3) | \

    INT_MASK(INT_SINGLE_STEP_2) | \

    INT_MASK(INT_SINGLE_STEP_1) | \

    INT_MASK(INT_SINGLE_STEP_0) | \

    INT_MASK(INT_IDN_COMPLETE) | \

    INT_MASK(INT_UDN_COMPLETE) | \

    INT_MASK(INT_ITLB_MISS) | \

    INT_MASK(INT_ILL) | \

    INT_MASK(INT_GPV) | \

    INT_MASK(INT_IDN_ACCESS) | \

    INT_MASK(INT_UDN_ACCESS) | \

    INT_MASK(INT_SWINT_3) | \

    INT_MASK(INT_SWINT_2) | \

    INT_MASK(INT_SWINT_1) | \

    INT_MASK(INT_SWINT_0) | \

    INT_MASK(INT_ILL_TRANS) | \

    INT_MASK(INT_UNALIGN_DATA) | \

    INT_MASK(INT_DTLB_MISS) | \

    INT_MASK(INT_DTLB_ACCESS) | \

    0)

#define NON_SYNC_INTERRUPTS ( \

    INT_MASK(INT_MEM_ERROR) | \

    INT_MASK(INT_IDN_FIREWALL) | \

    INT_MASK(INT_UDN_FIREWALL) | \

    INT_MASK(INT_TILE_TIMER) | \

    INT_MASK(INT_AUX_TILE_TIMER) | \

    INT_MASK(INT_IDN_TIMER) | \

    INT_MASK(INT_UDN_TIMER) | \

    INT_MASK(INT_IDN_AVAIL) | \

    INT_MASK(INT_UDN_AVAIL) | \

    INT_MASK(INT_IPI_3) | \

    INT_MASK(INT_IPI_2) | \

    INT_MASK(INT_IPI_1) | \

    INT_MASK(INT_IPI_0) | \

    INT_MASK(INT_PERF_COUNT) | \

    INT_MASK(INT_AUX_PERF_COUNT) | \

    INT_MASK(INT_INTCTRL_3) | \

    INT_MASK(INT_INTCTRL_2) | \

    INT_MASK(INT_INTCTRL_1) | \

    INT_MASK(INT_INTCTRL_0) | \

    INT_MASK(INT_BOOT_ACCESS) | \

    INT_MASK(INT_WORLD_ACCESS) | \

    INT_MASK(INT_I_ASID) | \

    INT_MASK(INT_D_ASID) | \

    INT_MASK(INT_DOUBLE_FAULT) | \

    0)

#endif /* !__ASSEMBLER__ */

#endif /* !__ARCH_INTERRUPTS_H__ */

arch/tile/include/arch/spr_def_64.h

0 → 100644
+173 −0
Original line number Diff line number Diff line 
/*

 * Copyright 2011 Tilera Corporation. All Rights Reserved.

 *

 *   This program is free software; you can redistribute it and/or

 *   modify it under the terms of the GNU General Public License

 *   as published by the Free Software Foundation, version 2.

 *

 *   This program is distributed in the hope that it will be useful, but

 *   WITHOUT ANY WARRANTY; without even the implied warranty of

 *   MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or

 *   NON INFRINGEMENT.  See the GNU General Public License for

 *   more details.

 */



#ifndef __DOXYGEN__



#ifndef __ARCH_SPR_DEF_H__

#define __ARCH_SPR_DEF_H__



#define SPR_AUX_PERF_COUNT_0 0x2105

#define SPR_AUX_PERF_COUNT_1 0x2106

#define SPR_AUX_PERF_COUNT_CTL 0x2107

#define SPR_AUX_PERF_COUNT_STS 0x2108

#define SPR_CMPEXCH_VALUE 0x2780

#define SPR_CYCLE 0x2781

#define SPR_DONE 0x2705

#define SPR_DSTREAM_PF 0x2706

#define SPR_EVENT_BEGIN 0x2782

#define SPR_EVENT_END 0x2783

#define SPR_EX_CONTEXT_0_0 0x2580

#define SPR_EX_CONTEXT_0_1 0x2581

#define SPR_EX_CONTEXT_0_1__PL_SHIFT 0

#define SPR_EX_CONTEXT_0_1__PL_RMASK 0x3

#define SPR_EX_CONTEXT_0_1__PL_MASK  0x3

#define SPR_EX_CONTEXT_0_1__ICS_SHIFT 2

#define SPR_EX_CONTEXT_0_1__ICS_RMASK 0x1

#define SPR_EX_CONTEXT_0_1__ICS_MASK  0x4

#define SPR_EX_CONTEXT_1_0 0x2480

#define SPR_EX_CONTEXT_1_1 0x2481

#define SPR_EX_CONTEXT_1_1__PL_SHIFT 0

#define SPR_EX_CONTEXT_1_1__PL_RMASK 0x3

#define SPR_EX_CONTEXT_1_1__PL_MASK  0x3

#define SPR_EX_CONTEXT_1_1__ICS_SHIFT 2

#define SPR_EX_CONTEXT_1_1__ICS_RMASK 0x1

#define SPR_EX_CONTEXT_1_1__ICS_MASK  0x4

#define SPR_EX_CONTEXT_2_0 0x2380

#define SPR_EX_CONTEXT_2_1 0x2381

#define SPR_EX_CONTEXT_2_1__PL_SHIFT 0

#define SPR_EX_CONTEXT_2_1__PL_RMASK 0x3

#define SPR_EX_CONTEXT_2_1__PL_MASK  0x3

#define SPR_EX_CONTEXT_2_1__ICS_SHIFT 2

#define SPR_EX_CONTEXT_2_1__ICS_RMASK 0x1

#define SPR_EX_CONTEXT_2_1__ICS_MASK  0x4

#define SPR_FAIL 0x2707

#define SPR_ILL_TRANS_REASON__I_STREAM_VA_RMASK 0x1

#define SPR_INTCTRL_0_STATUS 0x2505

#define SPR_INTCTRL_1_STATUS 0x2405

#define SPR_INTCTRL_2_STATUS 0x2305

#define SPR_INTERRUPT_CRITICAL_SECTION 0x2708

#define SPR_INTERRUPT_MASK_0 0x2506

#define SPR_INTERRUPT_MASK_1 0x2406

#define SPR_INTERRUPT_MASK_2 0x2306

#define SPR_INTERRUPT_MASK_RESET_0 0x2507

#define SPR_INTERRUPT_MASK_RESET_1 0x2407

#define SPR_INTERRUPT_MASK_RESET_2 0x2307

#define SPR_INTERRUPT_MASK_SET_0 0x2508

#define SPR_INTERRUPT_MASK_SET_1 0x2408

#define SPR_INTERRUPT_MASK_SET_2 0x2308

#define SPR_INTERRUPT_VECTOR_BASE_0 0x2509

#define SPR_INTERRUPT_VECTOR_BASE_1 0x2409

#define SPR_INTERRUPT_VECTOR_BASE_2 0x2309

#define SPR_INTERRUPT_VECTOR_BASE_3 0x2209

#define SPR_IPI_EVENT_0 0x1f05

#define SPR_IPI_EVENT_1 0x1e05

#define SPR_IPI_EVENT_2 0x1d05

#define SPR_IPI_EVENT_RESET_0 0x1f06

#define SPR_IPI_EVENT_RESET_1 0x1e06

#define SPR_IPI_EVENT_RESET_2 0x1d06

#define SPR_IPI_EVENT_SET_0 0x1f07

#define SPR_IPI_EVENT_SET_1 0x1e07

#define SPR_IPI_EVENT_SET_2 0x1d07

#define SPR_IPI_MASK_0 0x1f08

#define SPR_IPI_MASK_1 0x1e08

#define SPR_IPI_MASK_2 0x1d08

#define SPR_IPI_MASK_RESET_0 0x1f09

#define SPR_IPI_MASK_RESET_1 0x1e09

#define SPR_IPI_MASK_RESET_2 0x1d09

#define SPR_IPI_MASK_SET_0 0x1f0a

#define SPR_IPI_MASK_SET_1 0x1e0a

#define SPR_IPI_MASK_SET_2 0x1d0a

#define SPR_MPL_AUX_TILE_TIMER_SET_0 0x1700

#define SPR_MPL_AUX_TILE_TIMER_SET_1 0x1701

#define SPR_MPL_AUX_TILE_TIMER_SET_2 0x1702

#define SPR_MPL_INTCTRL_0_SET_0 0x2500

#define SPR_MPL_INTCTRL_0_SET_1 0x2501

#define SPR_MPL_INTCTRL_0_SET_2 0x2502

#define SPR_MPL_INTCTRL_1_SET_0 0x2400

#define SPR_MPL_INTCTRL_1_SET_1 0x2401

#define SPR_MPL_INTCTRL_1_SET_2 0x2402

#define SPR_MPL_INTCTRL_2_SET_0 0x2300

#define SPR_MPL_INTCTRL_2_SET_1 0x2301

#define SPR_MPL_INTCTRL_2_SET_2 0x2302

#define SPR_MPL_UDN_ACCESS_SET_0 0x0b00

#define SPR_MPL_UDN_ACCESS_SET_1 0x0b01

#define SPR_MPL_UDN_ACCESS_SET_2 0x0b02

#define SPR_MPL_UDN_AVAIL_SET_0 0x1b00

#define SPR_MPL_UDN_AVAIL_SET_1 0x1b01

#define SPR_MPL_UDN_AVAIL_SET_2 0x1b02

#define SPR_MPL_UDN_COMPLETE_SET_0 0x0600

#define SPR_MPL_UDN_COMPLETE_SET_1 0x0601

#define SPR_MPL_UDN_COMPLETE_SET_2 0x0602

#define SPR_MPL_UDN_FIREWALL_SET_0 0x1500

#define SPR_MPL_UDN_FIREWALL_SET_1 0x1501

#define SPR_MPL_UDN_FIREWALL_SET_2 0x1502

#define SPR_MPL_UDN_TIMER_SET_0 0x1900

#define SPR_MPL_UDN_TIMER_SET_1 0x1901

#define SPR_MPL_UDN_TIMER_SET_2 0x1902

#define SPR_MPL_WORLD_ACCESS_SET_0 0x2700

#define SPR_MPL_WORLD_ACCESS_SET_1 0x2701

#define SPR_MPL_WORLD_ACCESS_SET_2 0x2702

#define SPR_PASS 0x2709

#define SPR_PERF_COUNT_0 0x2005

#define SPR_PERF_COUNT_1 0x2006

#define SPR_PERF_COUNT_CTL 0x2007

#define SPR_PERF_COUNT_DN_CTL 0x2008

#define SPR_PERF_COUNT_STS 0x2009

#define SPR_PROC_STATUS 0x2784

#define SPR_SIM_CONTROL 0x2785

#define SPR_SINGLE_STEP_CONTROL_0 0x0405

#define SPR_SINGLE_STEP_CONTROL_0__CANCELED_MASK  0x1

#define SPR_SINGLE_STEP_CONTROL_0__INHIBIT_MASK  0x2

#define SPR_SINGLE_STEP_CONTROL_1 0x0305

#define SPR_SINGLE_STEP_CONTROL_1__CANCELED_MASK  0x1

#define SPR_SINGLE_STEP_CONTROL_1__INHIBIT_MASK  0x2

#define SPR_SINGLE_STEP_CONTROL_2 0x0205

#define SPR_SINGLE_STEP_CONTROL_2__CANCELED_MASK  0x1

#define SPR_SINGLE_STEP_CONTROL_2__INHIBIT_MASK  0x2

#define SPR_SINGLE_STEP_EN_0_0 0x250a

#define SPR_SINGLE_STEP_EN_0_1 0x240a

#define SPR_SINGLE_STEP_EN_0_2 0x230a

#define SPR_SINGLE_STEP_EN_1_0 0x250b

#define SPR_SINGLE_STEP_EN_1_1 0x240b

#define SPR_SINGLE_STEP_EN_1_2 0x230b

#define SPR_SINGLE_STEP_EN_2_0 0x250c

#define SPR_SINGLE_STEP_EN_2_1 0x240c

#define SPR_SINGLE_STEP_EN_2_2 0x230c

#define SPR_SYSTEM_SAVE_0_0 0x2582

#define SPR_SYSTEM_SAVE_0_1 0x2583

#define SPR_SYSTEM_SAVE_0_2 0x2584

#define SPR_SYSTEM_SAVE_0_3 0x2585

#define SPR_SYSTEM_SAVE_1_0 0x2482

#define SPR_SYSTEM_SAVE_1_1 0x2483

#define SPR_SYSTEM_SAVE_1_2 0x2484

#define SPR_SYSTEM_SAVE_1_3 0x2485

#define SPR_SYSTEM_SAVE_2_0 0x2382

#define SPR_SYSTEM_SAVE_2_1 0x2383

#define SPR_SYSTEM_SAVE_2_2 0x2384

#define SPR_SYSTEM_SAVE_2_3 0x2385

#define SPR_TILE_COORD 0x270b

#define SPR_TILE_RTF_HWM 0x270c

#define SPR_TILE_TIMER_CONTROL 0x1605

#define SPR_UDN_AVAIL_EN 0x1b05

#define SPR_UDN_DATA_AVAIL 0x0b80

#define SPR_UDN_DEADLOCK_TIMEOUT 0x1906

#define SPR_UDN_DEMUX_COUNT_0 0x0b05

#define SPR_UDN_DEMUX_COUNT_1 0x0b06

#define SPR_UDN_DEMUX_COUNT_2 0x0b07

#define SPR_UDN_DEMUX_COUNT_3 0x0b08

#define SPR_UDN_DIRECTION_PROTECT 0x1505



#endif /* !defined(__ARCH_SPR_DEF_H__) */



#endif /* !defined(__DOXYGEN__) */