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Commit 18a8cd63 authored by David Daney's avatar David Daney Committed by Ralf Baechle
Browse files

MIPS: Add minimal support for OCTEON3 to c-r4k.c 



These are needed to boot a generic mips64r2 kernel on OCTEONIII.

Signed-off-by: default avatarDavid Daney <david.daney@cavium.com>
Signed-off-by: default avatarAndreas Herrmann <andreas.herrmann@caviumnetworks.com>
Cc: linux-mips@linux-mips.org
Cc: James Hogan <james.hogan@imgtec.com>
Cc: kvm@vger.kernel.org
Patchwork: https://patchwork.linux-mips.org/patch/7003/


Signed-off-by: default avatarRalf Baechle <ralf@linux-mips.org>
parent 35d04706

arch/mips/include/asm/r4kcache.h

+2 −0
Original line number Diff line number Diff line
@@ -523,6 +523,8 @@ __BUILD_BLAST_CACHE(s, scache, Index_Writeback_Inv_SD, Hit_Writeback_Inv_SD, 32, 
__BUILD_BLAST_CACHE(d, dcache, Index_Writeback_Inv_D, Hit_Writeback_Inv_D, 64, )

__BUILD_BLAST_CACHE(i, icache, Index_Invalidate_I, Hit_Invalidate_I, 64, )

__BUILD_BLAST_CACHE(s, scache, Index_Writeback_Inv_SD, Hit_Writeback_Inv_SD, 64, )

__BUILD_BLAST_CACHE(d, dcache, Index_Writeback_Inv_D, Hit_Writeback_Inv_D, 128, )

__BUILD_BLAST_CACHE(i, icache, Index_Invalidate_I, Hit_Invalidate_I, 128, )

__BUILD_BLAST_CACHE(s, scache, Index_Writeback_Inv_SD, Hit_Writeback_Inv_SD, 128, )



__BUILD_BLAST_CACHE(inv_d, dcache, Index_Writeback_Inv_D, Hit_Invalidate_D, 16, )

arch/mips/mm/c-r4k.c

+44 −4
Original line number Diff line number Diff line
@@ -109,18 +109,34 @@ static inline void r4k_blast_dcache_page_dc64(unsigned long addr) 
	blast_dcache64_page(addr);

}



static inline void r4k_blast_dcache_page_dc128(unsigned long addr)

{

	blast_dcache128_page(addr);

}



static void r4k_blast_dcache_page_setup(void)

{

	unsigned long  dc_lsize = cpu_dcache_line_size();



	if (dc_lsize == 0)

	switch (dc_lsize) {

	case 0:

		r4k_blast_dcache_page = (void *)cache_noop;

	else if (dc_lsize == 16)

		break;

	case 16:

		r4k_blast_dcache_page = blast_dcache16_page;

	else if (dc_lsize == 32)

		break;

	case 32:

		r4k_blast_dcache_page = r4k_blast_dcache_page_dc32;

	else if (dc_lsize == 64)

		break;

	case 64:

		r4k_blast_dcache_page = r4k_blast_dcache_page_dc64;

		break;

	case 128:

		r4k_blast_dcache_page = r4k_blast_dcache_page_dc128;

		break;

	default:

		break;

	}

}



#ifndef CONFIG_EVA
@@ -159,6 +175,8 @@ static void r4k_blast_dcache_page_indexed_setup(void) 
		r4k_blast_dcache_page_indexed = blast_dcache32_page_indexed;

	else if (dc_lsize == 64)

		r4k_blast_dcache_page_indexed = blast_dcache64_page_indexed;

	else if (dc_lsize == 128)

		r4k_blast_dcache_page_indexed = blast_dcache128_page_indexed;

}



void (* r4k_blast_dcache)(void);
@@ -176,6 +194,8 @@ static void r4k_blast_dcache_setup(void) 
		r4k_blast_dcache = blast_dcache32;

	else if (dc_lsize == 64)

		r4k_blast_dcache = blast_dcache64;

	else if (dc_lsize == 128)

		r4k_blast_dcache = blast_dcache128;

}



/* force code alignment (used for TX49XX_ICACHE_INDEX_INV_WAR) */
@@ -265,6 +285,8 @@ static void r4k_blast_icache_page_setup(void) 
		r4k_blast_icache_page = blast_icache32_page;

	else if (ic_lsize == 64)

		r4k_blast_icache_page = blast_icache64_page;

	else if (ic_lsize == 128)

		r4k_blast_icache_page = blast_icache128_page;

}



#ifndef CONFIG_EVA
@@ -338,6 +360,8 @@ static void r4k_blast_icache_setup(void) 
			r4k_blast_icache = blast_icache32;

	} else if (ic_lsize == 64)

		r4k_blast_icache = blast_icache64;

	else if (ic_lsize == 128)

		r4k_blast_icache = blast_icache128;

}



static void (* r4k_blast_scache_page)(unsigned long addr);
@@ -1094,6 +1118,21 @@ static void probe_pcache(void) 
		c->dcache.waybit = 0;

		break;



	case CPU_CAVIUM_OCTEON3:

		/* For now lie about the number of ways. */

		c->icache.linesz = 128;

		c->icache.sets = 16;

		c->icache.ways = 8;

		c->icache.flags |= MIPS_CACHE_VTAG;

		icache_size = c->icache.sets * c->icache.ways * c->icache.linesz;



		c->dcache.linesz = 128;

		c->dcache.ways = 8;

		c->dcache.sets = 8;

		dcache_size = c->dcache.sets * c->dcache.ways * c->dcache.linesz;

		c->options |= MIPS_CPU_PREFETCH;

		break;



	default:

		if (!(config & MIPS_CONF_M))

			panic("Don't know how to probe P-caches on this cpu.");
@@ -1414,6 +1453,7 @@ static void setup_scache(void) 
		loongson3_sc_init();

		return;



	case CPU_CAVIUM_OCTEON3:

	case CPU_XLP:

		/* don't need to worry about L2, fully coherent */

		return;