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Commit 18280eda authored by David Daney's avatar David Daney Committed by Ralf Baechle
Browse files

MIPS: Add code for new system 'paravirt' 



For para-virtualized guests running under KVM or other equivalent
hypervisor.

Signed-off-by: default avatarDavid Daney <david.daney@cavium.com>
Signed-off-by: default avatarAndreas Herrmann <andreas.herrmann@caviumnetworks.com>
Cc: linux-mips@linux-mips.org
Cc: James Hogan <james.hogan@imgtec.com>
Cc: kvm@vger.kernel.org
Patchwork: https://patchwork.linux-mips.org/patch/7004/


Signed-off-by: default avatarRalf Baechle <ralf@linux-mips.org>
parent 90dfdc7c

arch/mips/include/asm/mach-paravirt/cpu-feature-overrides.h

0 → 100644
+36 −0
Original line number Diff line number Diff line 
/*

 * This file is subject to the terms and conditions of the GNU General Public

 * License.  See the file "COPYING" in the main directory of this archive

 * for more details.

 *

 * Copyright (C) 2013 Cavium, Inc.

 */

#ifndef __ASM_MACH_PARAVIRT_CPU_FEATURE_OVERRIDES_H

#define __ASM_MACH_PARAVIRT_CPU_FEATURE_OVERRIDES_H



#define cpu_has_4kex		1

#define cpu_has_3k_cache	0

#define cpu_has_tx39_cache	0

#define cpu_has_counter		1

#define cpu_has_llsc		1

/*

 * We Disable LL/SC on non SMP systems as it is faster to disable

 * interrupts for atomic access than a LL/SC.

 */

#ifdef CONFIG_SMP

# define kernel_uses_llsc	1

#else

# define kernel_uses_llsc	0

#endif



#ifdef CONFIG_CPU_CAVIUM_OCTEON

#define cpu_dcache_line_size()	128

#define cpu_icache_line_size()	128

#define cpu_has_octeon_cache	1

#define cpu_has_4k_cache	0

#else

#define cpu_has_octeon_cache	0

#define cpu_has_4k_cache	1

#endif



#endif /* __ASM_MACH_PARAVIRT_CPU_FEATURE_OVERRIDES_H */

arch/mips/include/asm/mach-paravirt/irq.h

0 → 100644
+19 −0
Original line number Diff line number Diff line 
/*

 * This file is subject to the terms and conditions of the GNU General Public

 * License.  See the file "COPYING" in the main directory of this archive

 * for more details.

 *

 * Copyright (C) 2013 Cavium, Inc.

 */

#ifndef __ASM_MACH_PARAVIRT_IRQ_H__

#define  __ASM_MACH_PARAVIRT_IRQ_H__



#define NR_IRQS 64

#define MIPS_CPU_IRQ_BASE 1



#define MIPS_IRQ_PCIA (MIPS_CPU_IRQ_BASE + 8)



#define MIPS_IRQ_MBOX0 (MIPS_CPU_IRQ_BASE + 32)

#define MIPS_IRQ_MBOX1 (MIPS_CPU_IRQ_BASE + 33)



#endif /* __ASM_MACH_PARAVIRT_IRQ_H__ */

arch/mips/include/asm/mach-paravirt/kernel-entry-init.h

0 → 100644
+50 −0
Original line number Diff line number Diff line 
/*

 * This file is subject to the terms and conditions of the GNU General Public

 * License.  See the file "COPYING" in the main directory of this archive

 * for more details.

 *

 * Copyright (C) 2013 Cavium, Inc

 */

#ifndef __ASM_MACH_PARAVIRT_KERNEL_ENTRY_H

#define __ASM_MACH_PARAVIRT_KERNEL_ENTRY_H



#define CP0_EBASE $15, 1



	.macro  kernel_entry_setup

	mfc0	t0, CP0_EBASE

	andi	t0, t0, 0x3ff		# CPUNum

	beqz	t0, 1f

	# CPUs other than zero goto smp_bootstrap

	j	smp_bootstrap



1:

	.endm



/*

 * Do SMP slave processor setup necessary before we can safely execute

 * C code.

 */

	.macro  smp_slave_setup

	mfc0	t0, CP0_EBASE

	andi	t0, t0, 0x3ff		# CPUNum

	slti	t1, t0, NR_CPUS

	bnez	t1, 1f

2:

	di

	wait

	b	2b			# Unknown CPU, loop forever.

1:

	PTR_LA	t1, paravirt_smp_sp

	PTR_SLL	t0, PTR_SCALESHIFT

	PTR_ADDU t1, t1, t0

3:

	PTR_L	sp, 0(t1)

	beqz	sp, 3b			# Spin until told to proceed.



	PTR_LA	t1, paravirt_smp_gp

	PTR_ADDU t1, t1, t0

	sync

	PTR_L	gp, 0(t1)

	.endm



#endif /* __ASM_MACH_PARAVIRT_KERNEL_ENTRY_H */

arch/mips/include/asm/mach-paravirt/war.h

0 → 100644
+25 −0
Original line number Diff line number Diff line 
/*

 * This file is subject to the terms and conditions of the GNU General Public

 * License.  See the file "COPYING" in the main directory of this archive

 * for more details.

 *

 * Copyright (C) 2002, 2004, 2007 by Ralf Baechle <ralf@linux-mips.org>

 * Copyright (C) 2013 Cavium Networks <support@caviumnetworks.com>

 */

#ifndef __ASM_MIPS_MACH_PARAVIRT_WAR_H

#define __ASM_MIPS_MACH_PARAVIRT_WAR_H



#define R4600_V1_INDEX_ICACHEOP_WAR	0

#define R4600_V1_HIT_CACHEOP_WAR	0

#define R4600_V2_HIT_CACHEOP_WAR	0

#define R5432_CP0_INTERRUPT_WAR		0

#define BCM1250_M3_WAR			0

#define SIBYTE_1956_WAR			0

#define MIPS4K_ICACHE_REFILL_WAR	0

#define MIPS_CACHE_SYNC_WAR		0

#define TX49XX_ICACHE_INDEX_INV_WAR	0

#define ICACHE_REFILLS_WORKAROUND_WAR	0

#define R10000_LLSC_WAR			0

#define MIPS34K_MISSED_ITLB_WAR		0



#endif /* __ASM_MIPS_MACH_PARAVIRT_WAR_H */

arch/mips/mm/tlbex.c

+2 −6
Original line number Diff line number Diff line
@@ -1250,17 +1250,13 @@ static void build_r4000_tlb_refill_handler(void) 
	unsigned int final_len;

	struct mips_huge_tlb_info htlb_info __maybe_unused;

	enum vmalloc64_mode vmalloc_mode __maybe_unused;

#ifdef CONFIG_64BIT

	bool is64bit = true;

#else

	bool is64bit = false;

#endif



	memset(tlb_handler, 0, sizeof(tlb_handler));

	memset(labels, 0, sizeof(labels));

	memset(relocs, 0, sizeof(relocs));

	memset(final_handler, 0, sizeof(final_handler));



	if (is64bit && (scratch_reg >= 0 || scratchpad_available()) && use_bbit_insns()) {

	if (IS_ENABLED(CONFIG_64BIT) && (scratch_reg >= 0 || scratchpad_available()) && use_bbit_insns()) {

		htlb_info = build_fast_tlb_refill_handler(&p, &l, &r, K0, K1,

							  scratch_reg);

		vmalloc_mode = refill_scratch;