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Commit 1781460c authored by Geert Uytterhoeven's avatar Geert Uytterhoeven Committed by Simon Horman
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ARM: dts: lager: Enable SCIF_CLK frequency and pins 



Add and enable the external crystal for the SCIF_CLK and its pinctrl, to
be used by the Baud Rate Generator for External Clock (BRG) on (H)SCIF.

This increases the range and accuracy of supported baud rates.

Signed-off-by: default avatarGeert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: default avatarSimon Horman <horms+renesas@verge.net.au>
parent 338f7ebf

arch/arm/boot/dts/r8a7790-lager.dts

+13 −0
Original line number Diff line number Diff line
@@ -291,6 +291,9 @@ 
};



&pfc {

	pinctrl-0 = <&scif_clk_pins>;

	pinctrl-names = "default";



	du_pins: du {

		renesas,groups = "du_rgb666", "du_sync_1", "du_clk_out_0";

		renesas,function = "du";
@@ -301,6 +304,11 @@ 
		renesas,function = "scif0";

	};



	scif_clk_pins: scif_clk {

		renesas,groups = "scif_clk";

		renesas,function = "scif_clk";

	};



	ether_pins: ether {

		renesas,groups = "eth_link", "eth_mdio", "eth_rmii";

		renesas,function = "eth";
@@ -485,6 +493,11 @@ 
	status = "okay";

};



&scif_clk {

	clock-frequency = <14745600>;

	status = "okay";

};



&msiof1 {

	pinctrl-0 = <&msiof1_pins>;

	pinctrl-names = "default";