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Commit 168f1a71 authored by Linus Torvalds's avatar Linus Torvalds
Browse files

Merge branch 'x86-asm-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip 

Pull x86 asm updates from Ingo Molnar:
 "The main changes in this cycle were:

   - MSR access API fixes and enhancements (Andy Lutomirski)

   - early exception handling improvements (Andy Lutomirski)

   - user-space FS/GS prctl usage fixes and improvements (Andy
     Lutomirski)

   - Remove the cpu_has_*() APIs and replace them with equivalents
     (Borislav Petkov)

   - task switch micro-optimization (Brian Gerst)

   - 32-bit entry code simplification (Denys Vlasenko)

   - enhance PAT handling in enumated CPUs (Toshi Kani)

  ... and lots of other cleanups/fixlets"

* 'x86-asm-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip: (70 commits)
  x86/arch_prctl/64: Restore accidentally removed put_cpu() in ARCH_SET_GS
  x86/entry/32: Remove asmlinkage_protect()
  x86/entry/32: Remove GET_THREAD_INFO() from entry code
  x86/entry, sched/x86: Don't save/restore EFLAGS on task switch
  x86/asm/entry/32: Simplify pushes of zeroed pt_regs->REGs
  selftests/x86/ldt_gdt: Test set_thread_area() deletion of an active segment
  x86/tls: Synchronize segment registers in set_thread_area()
  x86/asm/64: Rename thread_struct's fs and gs to fsbase and gsbase
  x86/arch_prctl/64: Remove FSBASE/GSBASE < 4G optimization
  x86/segments/64: When load_gs_index fails, clear the base
  x86/segments/64: When loadsegment(fs, ...) fails, clear the base
  x86/asm: Make asm/alternative.h safe from assembly
  x86/asm: Stop depending on ptrace.h in alternative.h
  x86/entry: Rename is_{ia32,x32}_task() to in_{ia32,x32}_syscall()
  x86/asm: Make sure verify_cpu() has a good stack
  x86/extable: Add a comment about early exception handlers
  x86/msr: Set the return value to zero when native_rdmsr_safe() fails
  x86/paravirt: Make "unsafe" MSR accesses unsafe even if PARAVIRT=y
  x86/paravirt: Add paravirt_{read,write}_msr()
  x86/msr: Carry on after a non-"safe" MSR access fails
  ...
parents 825a3b26 4afd0565

Documentation/x86/pat.txt

+32 −0
Original line number Diff line number Diff line
@@ -196,3 +196,35 @@ Another, more verbose way of getting PAT related debug messages is with 
"debugpat" boot parameter. With this parameter, various debug messages are

printed to dmesg log.



PAT Initialization

------------------



The following table describes how PAT is initialized under various

configurations. The PAT MSR must be updated by Linux in order to support WC

and WT attributes. Otherwise, the PAT MSR has the value programmed in it

by the firmware. Note, Xen enables WC attribute in the PAT MSR for guests.



 MTRR PAT   Call Sequence               PAT State  PAT MSR

 =========================================================

 E    E     MTRR -> PAT init            Enabled    OS

 E    D     MTRR -> PAT init            Disabled    -

 D    E     MTRR -> PAT disable         Disabled   BIOS

 D    D     MTRR -> PAT disable         Disabled    -

 -    np/E  PAT  -> PAT disable         Disabled   BIOS

 -    np/D  PAT  -> PAT disable         Disabled    -

 E    !P/E  MTRR -> PAT init            Disabled   BIOS

 D    !P/E  MTRR -> PAT disable         Disabled   BIOS

 !M   !P/E  MTRR stub -> PAT disable    Disabled   BIOS



 Legend

 ------------------------------------------------

 E         Feature enabled in CPU

 D	   Feature disabled/unsupported in CPU

 np	   "nopat" boot option specified

 !P	   CONFIG_X86_PAT option unset

 !M	   CONFIG_MTRR option unset

 Enabled   PAT state set to enabled

 Disabled  PAT state set to disabled

 OS        PAT initializes PAT MSR with OS setting

 BIOS      PAT keeps PAT MSR with BIOS setting

arch/ia64/include/asm/iommu.h

+0 −1
Original line number Diff line number Diff line 
#ifndef _ASM_IA64_IOMMU_H

#define _ASM_IA64_IOMMU_H 1



#define cpu_has_x2apic 0

/* 10 seconds */

#define DMAR_OPERATION_TIMEOUT (((cycles_t) local_cpu_data->itc_freq)*10)

arch/x86/crypto/aesni-intel_glue.c

+1 −1
Original line number Diff line number Diff line
@@ -1477,7 +1477,7 @@ static int __init aesni_init(void) 
	}

	aesni_ctr_enc_tfm = aesni_ctr_enc;

#ifdef CONFIG_AS_AVX

	if (cpu_has_avx) {

	if (boot_cpu_has(X86_FEATURE_AVX)) {

		/* optimize performance of ctr mode encryption transform */

		aesni_ctr_enc_tfm = aesni_ctr_enc_avx_tfm;

		pr_info("AES CTR mode by8 optimization enabled\n");

arch/x86/crypto/camellia_aesni_avx2_glue.c

+4 −1
Original line number Diff line number Diff line
@@ -562,7 +562,10 @@ static int __init camellia_aesni_init(void) 
{

	const char *feature_name;



	if (!cpu_has_avx2 || !cpu_has_avx || !cpu_has_aes || !cpu_has_osxsave) {

	if (!boot_cpu_has(X86_FEATURE_AVX) ||

	    !boot_cpu_has(X86_FEATURE_AVX2) ||

	    !boot_cpu_has(X86_FEATURE_AES) ||

	    !boot_cpu_has(X86_FEATURE_OSXSAVE)) {

		pr_info("AVX2 or AES-NI instructions are not detected.\n");

		return -ENODEV;

	}

arch/x86/crypto/camellia_aesni_avx_glue.c

+3 −1
Original line number Diff line number Diff line
@@ -554,7 +554,9 @@ static int __init camellia_aesni_init(void) 
{

	const char *feature_name;



	if (!cpu_has_avx || !cpu_has_aes || !cpu_has_osxsave) {

	if (!boot_cpu_has(X86_FEATURE_AVX) ||

	    !boot_cpu_has(X86_FEATURE_AES) ||

	    !boot_cpu_has(X86_FEATURE_OSXSAVE)) {

		pr_info("AVX or AES-NI instructions are not detected.\n");

		return -ENODEV;

	}