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Commit 159f9875 authored by Ville Syrjälä's avatar Ville Syrjälä Committed by Daniel Vetter
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drm/i915: FBC_CONTROL2 is gen4 only 



Gen2 and gen3 don't have the FBC_CONTROL2 register, so don't
touch it.

Signed-off-by: default avatarVille Syrjälä <ville.syrjala@linux.intel.com>
Reviewed-by: default avatarImre Deak <imre.deak@intel.com>
Signed-off-by: default avatarDaniel Vetter <daniel.vetter@ffwll.ch>
parent 42a430f5

drivers/gpu/drm/i915/intel_pm.c

+10 −6
Original line number Diff line number Diff line
@@ -98,7 +98,7 @@ static void i8xx_enable_fbc(struct drm_crtc *crtc, unsigned long interval) 
	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);

	int cfb_pitch;

	int plane, i;

	u32 fbc_ctl, fbc_ctl2;

	u32 fbc_ctl;



	cfb_pitch = dev_priv->fbc.size / FBC_LL_SIZE;

	if (fb->pitches[0] < cfb_pitch)
@@ -115,11 +115,15 @@ static void i8xx_enable_fbc(struct drm_crtc *crtc, unsigned long interval) 
	for (i = 0; i < (FBC_LL_SIZE / 32) + 1; i++)

		I915_WRITE(FBC_TAG + (i * 4), 0);



	if (IS_GEN4(dev)) {

		u32 fbc_ctl2;



		/* Set it up... */

		fbc_ctl2 = FBC_CTL_FENCE_DBL | FBC_CTL_IDLE_IMM | FBC_CTL_CPU_FENCE;

		fbc_ctl2 |= plane;

		I915_WRITE(FBC_CONTROL2, fbc_ctl2);

		I915_WRITE(FBC_FENCE_OFF, crtc->y);

	}



	/* enable it... */

	fbc_ctl = FBC_CTL_EN | FBC_CTL_PERIODIC;