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Commit 14fd8629 authored by Daniel Scheller's avatar Daniel Scheller Committed by Mauro Carvalho Chehab
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[media] dvb-frontends/cxd2841er: configurable IFAGCNEG 



Adds a flag to enable or disable the IFAGCNEG bit in cxd2841er_init_tc().

Signed-off-by: default avatarDaniel Scheller <d.scheller@gmx.net>
Acked-by: default avatarAbylay Ospan <aospan@netup.ru>
Signed-off-by: default avatarMauro Carvalho Chehab <mchehab@s-opensource.com>
parent e3943aa6

drivers/media/dvb-frontends/cxd2841er.c

+3 −2
Original line number Original line Diff line number Diff line
@@ -3783,9 +3783,10 @@ static int cxd2841er_init_tc(struct dvb_frontend *fe) 
	dev_dbg(&priv->i2c->dev, "%s() bandwidth_hz=%d\n",

	dev_dbg(&priv->i2c->dev, "%s() bandwidth_hz=%d\n",

			__func__, p->bandwidth_hz);

			__func__, p->bandwidth_hz);

	cxd2841er_shutdown_to_sleep_tc(priv);

	cxd2841er_shutdown_to_sleep_tc(priv);

	/* SONY_DEMOD_CONFIG_IFAGCNEG = 1 */

	/* SONY_DEMOD_CONFIG_IFAGCNEG = 1 (0 for NO_AGCNEG */

	cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x10);

	cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x10);

	cxd2841er_set_reg_bits(priv, I2C_SLVT, 0xcb, 0x40, 0x40);

	cxd2841er_set_reg_bits(priv, I2C_SLVT, 0xcb,

		((priv->flags & CXD2841ER_NO_AGCNEG) ? 0x00 : 0x40), 0x40);

	/* SONY_DEMOD_CONFIG_IFAGC_ADC_FS = 0 */

	/* SONY_DEMOD_CONFIG_IFAGC_ADC_FS = 0 */

	cxd2841er_write_reg(priv, I2C_SLVT, 0xcd, 0x50);

	cxd2841er_write_reg(priv, I2C_SLVT, 0xcd, 0x50);

	/* SONY_DEMOD_CONFIG_PARALLEL_SEL = 1 */

	/* SONY_DEMOD_CONFIG_PARALLEL_SEL = 1 */

drivers/media/dvb-frontends/cxd2841er.h

+1 −0
Original line number Original line Diff line number Diff line
@@ -30,6 +30,7 @@ 
#define CXD2841ER_ASCOT		8	/* bit 3 */

#define CXD2841ER_ASCOT		8	/* bit 3 */

#define CXD2841ER_EARLY_TUNE	16	/* bit 4 */

#define CXD2841ER_EARLY_TUNE	16	/* bit 4 */

#define CXD2841ER_NO_WAIT_LOCK	32	/* bit 5 */

#define CXD2841ER_NO_WAIT_LOCK	32	/* bit 5 */

#define CXD2841ER_NO_AGCNEG	64	/* bit 6 */





enum cxd2841er_xtal {

enum cxd2841er_xtal {

	SONY_XTAL_20500, /* 20.5 MHz */

	SONY_XTAL_20500, /* 20.5 MHz */