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Commit 138ee7ee authored Jul 13, 2016 by Aneesh Kumar K.V Committed by Michael Ellerman Aug 01, 2016

powerpc/mm/hash: Add helper for finding SLBE LLP encoding



Replace opencoding of the same at multiple places with the helper.
No functional change with this patch.

Signed-off-by: Aneesh Kumar K.V <aneesh.kumar@linux.vnet.ibm.com>
Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>

parent 8cb8140c

arch/powerpc/include/asm/book3s/64/mmu-hash.h

+9 −0

Original line number	Original line	Diff line number	Diff line
	@@ -191,6 +191,15 @@ static inline unsigned int mmu_psize_to_shift(unsigned int mmu_psize)
	BUG();		BUG();
	}		}

			static inline unsigned long get_sllp_encoding(int psize)
			{
			unsigned long sllp;

			sllp = ((mmu_psize_defs[psize].sllp & SLB_VSID_L) >> 6) \|
			((mmu_psize_defs[psize].sllp & SLB_VSID_LP) >> 4);
			return sllp;
			}

	#endif /* __ASSEMBLY__ */		#endif /* __ASSEMBLY__ */

	/*		/*

arch/powerpc/include/asm/kvm_book3s_64.h

+1 −2

Original line number	Original line	Diff line number	Diff line
	@@ -181,8 +181,7 @@ static inline unsigned long compute_tlbie_rb(unsigned long v, unsigned long r,

	switch (b_psize) {		switch (b_psize) {
	case MMU_PAGE_4K:		case MMU_PAGE_4K:
	sllp = ((mmu_psize_defs[a_psize].sllp & SLB_VSID_L) >> 6) \|		sllp = get_sllp_encoding(a_psize);
	((mmu_psize_defs[a_psize].sllp & SLB_VSID_LP) >> 4);
	rb \|= sllp << 5; /* AP field */		rb \|= sllp << 5; /* AP field */
	rb \|= (va_low & 0x7ff) << 12; /* remaining 11 bits of AVA */		rb \|= (va_low & 0x7ff) << 12; /* remaining 11 bits of AVA */
	break;		break;

arch/powerpc/mm/hash_native_64.c

+2 −4

Original line number	Original line	Diff line number	Diff line
	@@ -72,8 +72,7 @@ static inline void __tlbie(unsigned long vpn, int psize, int apsize, int ssize)
	/* clear out bits after (52) [0....52.....63] */		/* clear out bits after (52) [0....52.....63] */
	va &= ~((1ul << (64 - 52)) - 1);		va &= ~((1ul << (64 - 52)) - 1);
	va \|= ssize << 8;		va \|= ssize << 8;
	sllp = ((mmu_psize_defs[apsize].sllp & SLB_VSID_L) >> 6) \|		sllp = get_sllp_encoding(apsize);
	((mmu_psize_defs[apsize].sllp & SLB_VSID_LP) >> 4);
	va \|= sllp << 5;		va \|= sllp << 5;
	asm volatile(ASM_FTR_IFCLR("tlbie %0,0", PPC_TLBIE(%1,%0), %2)		asm volatile(ASM_FTR_IFCLR("tlbie %0,0", PPC_TLBIE(%1,%0), %2)
	: : "r" (va), "r"(0), "i" (CPU_FTR_ARCH_206)		: : "r" (va), "r"(0), "i" (CPU_FTR_ARCH_206)
	@@ -122,8 +121,7 @@ static inline void __tlbiel(unsigned long vpn, int psize, int apsize, int ssize)
	/* clear out bits after(52) [0....52.....63] */		/* clear out bits after(52) [0....52.....63] */
	va &= ~((1ul << (64 - 52)) - 1);		va &= ~((1ul << (64 - 52)) - 1);
	va \|= ssize << 8;		va \|= ssize << 8;
	sllp = ((mmu_psize_defs[apsize].sllp & SLB_VSID_L) >> 6) \|		sllp = get_sllp_encoding(apsize);
	((mmu_psize_defs[apsize].sllp & SLB_VSID_LP) >> 4);
	va \|= sllp << 5;		va \|= sllp << 5;
	asm volatile(".long 0x7c000224 \| (%0 << 11) \| (0 << 21)"		asm volatile(".long 0x7c000224 \| (%0 << 11) \| (0 << 21)"
	: : "r"(va) : "memory");		: : "r"(va) : "memory");