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Commit 123267aa authored by Jingoo Han's avatar Jingoo Han Committed by Florian Tobias Schandinat
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video: exynos_dp: fix wrong DPCD address during Link Training 



Wrong DPCD addresses were used for clock recovery during Link Training.
The training pattern should be set by TRAINING_PATTERN_SET (0x102), while
voltage swing and pre-emphasis should be set by TRAINING_LANE0_SET (0x103).

Signed-off-by: default avatarJingoo Han <jg1.han@samsung.com>
Signed-off-by: default avatarFlorian Tobias Schandinat <FlorianSchandinat@gmx.de>
parent 2fe2d9f4

drivers/video/exynos/exynos_dp_core.c

+2 −2
Original line number Diff line number Diff line
@@ -304,7 +304,7 @@ static void exynos_dp_link_start(struct exynos_dp_device *dp) 
		buf[lane] = DPCD_PRE_EMPHASIS_PATTERN2_LEVEL0 |

			    DPCD_VOLTAGE_SWING_PATTERN1_LEVEL0;

	exynos_dp_write_bytes_to_dpcd(dp,

		DPCD_ADDR_TRAINING_PATTERN_SET,

		DPCD_ADDR_TRAINING_LANE0_SET,

		lane_count, buf);

}
@@ -504,7 +504,7 @@ static int exynos_dp_process_clock_recovery(struct exynos_dp_device *dp) 
		buf[0] = DPCD_SCRAMBLING_DISABLED |

			 DPCD_TRAINING_PATTERN_2;

		exynos_dp_write_byte_to_dpcd(dp,

			DPCD_ADDR_TRAINING_LANE0_SET,

			DPCD_ADDR_TRAINING_PATTERN_SET,

			buf[0]);



		for (lane = 0; lane < lane_count; lane++) {