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Commit 0eff4589 authored by Linus Torvalds's avatar Linus Torvalds
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Pull clk updates from Stephen Boyd:
 "It's the usual big pile of driver updates and additions, but we do
  have a couple core changes in here as well.

  Core:

   - CLK_IS_CRITICAL support has been added.  This should allow drivers
     to properly express that a certain clk should stay on even if their
     prepare/enable count drops to 0 (and in turn the parents of these
     clks should stay enabled).

   - A clk registration API has been added, clk_hw_register(), and an OF
     clk provider API has been added, of_clk_add_hw_provider().  These
     APIs have been put in place to further split clk providers from clk
     consumers, with the goal being to have clk providers never deal
     with struct clk pointers at all.  Conversion of provider drivers is
     on going.  clkdev has also gained support for registering clk_hw
     pointers directly so we can convert drivers that don't use
     devicetree.

  New Drivers:

   - Marvell ap806 and cp110 system controllers (with clks inside!)
   - Hisilicon Hi3519 clock and reset controller
   - Axis ARTPEC-6 clock controllers
   - Oxford Semiconductor OXNAS clock controllers
   - AXS10X I2S PLL
   - Rockchip RK3399 clock and reset controller

  Updates:

   - MMC2 and UART2 clks on Samsung Exynos 3250, ACLK on Samsung Exynos
     542x SoCs, and some more clk ID exporting for bus frequency scaling
   - Proper BCM2835 PCM clk support and various other clks
   - i.MX clk updates for i.MX6SX, i.MX7, and VF610
   - Renesas updates for R-Car H3
   - Tegra210 got updates for DisplayPort and HDMI 2.0
   - Rockchip driver refactorings and fixes due to adding RK3399 support"

* tag 'clk-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux: (139 commits)
  clk: fix critical clock locking
  clk: qcom: mmcc-8996: Remove clocks that should be controlled by RPM
  clk: ingenic: Allow divider value to be divided
  clk: sunxi: Add display and TCON0 clocks driver
  clk: rockchip: drop old_rate calculation on pll rate changes
  clk: rockchip: simplify GRF handling in pll clocks
  clk: rockchip: lookup General Register Files in rockchip_clk_init
  clk: rockchip: fix the rk3399 sdmmc sample / drv name
  clk: mvebu: new driver for Armada CP110 system controller
  dt-bindings: arm: add DT binding for Marvell CP110 system controller
  clk: mvebu: new driver for Armada AP806 system controller
  clk: hisilicon: add CRG driver for hi3519 soc
  clk: hisilicon: export some hisilicon APIs to modules
  reset: hisilicon: add reset controller driver for hisilicon SOCs
  clk: bcm/kona: Do not use sizeof on pointer type
  clk: qcom: msm8916: Fix crypto clock flags
  clk: nxp: lpc18xx: Initialize clk_init_data::flags to 0
  clk/axs10x: Add I2S PLL clock driver
  clk: imx7d: fix ahb clock mux 1
  clk: fix comment of devm_clk_hw_register()
  ...
parents 087afe8a ef56b79b
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Marvell Armada AP806 System Controller
======================================

The AP806 is one of the two core HW blocks of the Marvell Armada 7K/8K
SoCs. It contains a system controller, which provides a number
registers giving access to numerous features: clocks, pin-muxing and
many other SoC configuration items. This DT binding allows to describe
this system controller.

The Device Tree node representing the AP806 system controller provides
a number of clocks:

 - 0: clock of CPU cluster 0
 - 1: clock of CPU cluster 1
 - 2: fixed PLL at 1200 Mhz
 - 3: MSS clock, derived from the fixed PLL

Required properties:

 - compatible: must be:
     "marvell,ap806-system-controller", "syscon"
 - reg: register area of the AP806 system controller
 - #clock-cells: must be set to 1
 - clock-output-names: must be defined to:
    "ap-cpu-cluster-0", "ap-cpu-cluster-1", "ap-fixed", "ap-mss"

Example:

	syscon: system-controller@6f4000 {
		compatible = "marvell,ap806-system-controller", "syscon";
		#clock-cells = <1>;
		clock-output-names = "ap-cpu-cluster-0", "ap-cpu-cluster-1",
				     "ap-fixed", "ap-mss";
		reg = <0x6f4000 0x1000>;
	};
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Marvell Armada CP110 System Controller 0
========================================

The CP110 is one of the two core HW blocks of the Marvell Armada 7K/8K
SoCs. It contains two sets of system control registers, System
Controller 0 and System Controller 1. This Device Tree binding allows
to describe the first system controller, which provides registers to
configure various aspects of the SoC.

The Device Tree node representing this System Controller 0 provides a
number of clocks:

 - a set of core clocks
 - a set of gatable clocks

Those clocks can be referenced by other Device Tree nodes using two
cells:
 - The first cell must be 0 or 1. 0 for the core clocks and 1 for the
   gatable clocks.
 - The second cell identifies the particular core clock or gatable
   clocks.

The following clocks are available:
 - Core clocks
   - 0 0	APLL
   - 0 1	PPv2 core
   - 0 2	EIP
   - 0 3	Core
   - 0 4	NAND core
 - Gatable clocks
   - 1 0	Audio
   - 1 1	Comm Unit
   - 1 2	NAND
   - 1 3	PPv2
   - 1 4	SDIO
   - 1 5	MG Domain
   - 1 6	MG Core
   - 1 7	XOR1
   - 1 8	XOR0
   - 1 9	GOP DP
   - 1 11	PCIe x1 0
   - 1 12	PCIe x1 1
   - 1 13	PCIe x4
   - 1 14	PCIe / XOR
   - 1 15	SATA
   - 1 16	SATA USB
   - 1 17	Main
   - 1 18	SD/MMC
   - 1 21	Slow IO (SPI, NOR, BootROM, I2C, UART)
   - 1 22	USB3H0
   - 1 23	USB3H1
   - 1 24	USB3 Device
   - 1 25	EIP150
   - 1 26	EIP197

Required properties:

 - compatible: must be:
     "marvell,cp110-system-controller0", "syscon";
 - reg: register area of the CP110 system controller 0
 - #clock-cells: must be set to 2
 - core-clock-output-names must be set to:
	"cpm-apll", "cpm-ppv2-core", "cpm-eip", "cpm-core", "cpm-nand-core"
 - gate-clock-output-names must be set to:
	"cpm-audio", "cpm-communit", "cpm-nand", "cpm-ppv2", "cpm-sdio",
	"cpm-mg-domain", "cpm-mg-core", "cpm-xor1", "cpm-xor0", "cpm-gop-dp", "none",
	"cpm-pcie_x10", "cpm-pcie_x11", "cpm-pcie_x4", "cpm-pcie-xor", "cpm-sata",
	"cpm-sata-usb", "cpm-main", "cpm-sd-mmc", "none", "none", "cpm-slow-io",
	"cpm-usb3h0", "cpm-usb3h1", "cpm-usb3dev", "cpm-eip150", "cpm-eip197";

Example:

	cpm_syscon0: system-controller@440000 {
		compatible = "marvell,cp110-system-controller0", "syscon";
		reg = <0x440000 0x1000>;
		#clock-cells = <2>;
		core-clock-output-names = "cpm-apll", "cpm-ppv2-core", "cpm-eip", "cpm-core", "cpm-nand-core";
		gate-clock-output-names = "cpm-audio", "cpm-communit", "cpm-nand", "cpm-ppv2", "cpm-sdio",
			"cpm-mg-domain", "cpm-mg-core", "cpm-xor1", "cpm-xor0", "cpm-gop-dp", "none",
			"cpm-pcie_x10", "cpm-pcie_x11", "cpm-pcie_x4", "cpm-pcie-xor", "cpm-sata",
			"cpm-sata-usb", "cpm-main", "cpm-sd-mmc", "none", "none", "cpm-slow-io",
			"cpm-usb3h0", "cpm-usb3h1", "cpm-usb3dev", "cpm-eip150", "cpm-eip197";
	};
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* Clock bindings for Axis ARTPEC-6 chip

The bindings are based on the clock provider binding in
Documentation/devicetree/bindings/clock/clock-bindings.txt

External clocks:
----------------

There are two external inputs to the main clock controller which should be
provided using the common clock bindings.
- "sys_refclk": External 50 Mhz oscillator (required)
- "i2s_refclk": Alternate audio reference clock (optional).

Main clock controller
---------------------

Required properties:
- #clock-cells: Should be <1>
  See dt-bindings/clock/axis,artpec6-clkctrl.h for the list of valid identifiers.
- compatible: Should be "axis,artpec6-clkctrl"
- reg: Must contain the base address and length of the system controller
- clocks:  Must contain a phandle entry for each clock in clock-names
- clock-names: Must include the external oscillator ("sys_refclk"). Optional
  ones are the audio reference clock ("i2s_refclk") and the audio fractional
  dividers ("frac_clk0" and "frac_clk1").

Examples:

ext_clk: ext_clk {
	#clock-cells = <0>;
	compatible = "fixed-clock";
	clock-frequency = <50000000>;
};

clkctrl: clkctrl@f8000000 {
	#clock-cells = <1>;
	compatible = "axis,artpec6-clkctrl";
	reg = <0xf8000000 0x48>;
	clocks = <&ext_clk>;
	clock-names = "sys_refclk";
};
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Binding for the AXS10X I2S PLL clock

This binding uses the common clock binding[1].

[1] Documentation/devicetree/bindings/clock/clock-bindings.txt

Required properties:
- compatible: shall be "snps,axs10x-i2s-pll-clock"
- reg : address and length of the I2S PLL register set.
- clocks: shall be the input parent clock phandle for the PLL.
- #clock-cells: from common clock binding; Should always be set to 0.

Example:
	pll_clock: pll_clock {
		compatible = "fixed-clock";
		clock-frequency = <27000000>;
		#clock-cells = <0>;
	};

	i2s_clock@100a0 {
		compatible = "snps,axs10x-i2s-pll-clock";
		reg = <0x100a0 0x10>;
		clocks = <&pll_clock>;
		#clock-cells = <0>;
	};
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* Hisilicon Hi3519 Clock and Reset Generator(CRG)

The Hi3519 CRG module provides clock and reset signals to various
controllers within the SoC.

This binding uses the following bindings:
    Documentation/devicetree/bindings/clock/clock-bindings.txt
    Documentation/devicetree/bindings/reset/reset.txt

Required Properties:

- compatible: should be one of the following.
  - "hisilicon,hi3519-crg" - controller compatible with Hi3519 SoC.

- reg: physical base address of the controller and length of memory mapped
  region.

- #clock-cells: should be 1.

Each clock is assigned an identifier and client nodes use this identifier
to specify the clock which they consume.

All these identifier could be found in <dt-bindings/clock/hi3519-clock.h>.

- #reset-cells: should be 2.

A reset signal can be controlled by writing a bit register in the CRG module.
The reset specifier consists of two cells. The first cell represents the
register offset relative to the base address. The second cell represents the
bit index in the register.

Example: CRG nodes
CRG: clock-reset-controller@12010000 {
	compatible = "hisilicon,hi3519-crg";
	reg = <0x12010000 0x10000>;
	#clock-cells = <1>;
	#reset-cells = <2>;
};

Example: consumer nodes
i2c0: i2c@12110000 {
	compatible = "hisilicon,hi3519-i2c";
	reg = <0x12110000 0x1000>;
	clocks = <&CRG HI3519_I2C0_RST>;
	resets = <&CRG 0xe4 0>;
};
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