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Commit 0cfb26e1 authored by Thomas Abraham's avatar Thomas Abraham Committed by Kukjin Kim
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ARM: SAMSUNG: register uart clocks to clock lookup list 



Samsung uart driver lookups the clock using the connection id 'clk_uart_baud'.
The uart clocks for all Samsung platforms are reorganized to register them
with the lookup name as required by the uart driver.

Cc: Ben Dooks <ben-linux@fluff.org>
Signed-off-by: default avatarThomas Abraham <thomas.abraham@linaro.org>
Signed-off-by: default avatarKukjin Kim <kgene.kim@samsung.com>
parent c3310fbb

arch/arm/mach-exynos/clock.c

+66 −40
Original line number Original line Diff line number Diff line
@@ -1009,46 +1009,6 @@ static struct clksrc_clk clk_dout_mmc4 = { 




static struct clksrc_clk clksrcs[] = {

static struct clksrc_clk clksrcs[] = {

	{

	{

		.clk	= {

			.name		= "uclk1",

			.devname	= "s5pv210-uart.0",

			.enable		= exynos4_clksrc_mask_peril0_ctrl,

			.ctrlbit	= (1 << 0),

		},

		.sources = &clkset_group,

		.reg_src = { .reg = S5P_CLKSRC_PERIL0, .shift = 0, .size = 4 },

		.reg_div = { .reg = S5P_CLKDIV_PERIL0, .shift = 0, .size = 4 },

	}, {

		.clk		= {

			.name		= "uclk1",

			.devname	= "s5pv210-uart.1",

			.enable		= exynos4_clksrc_mask_peril0_ctrl,

			.ctrlbit	= (1 << 4),

		},

		.sources = &clkset_group,

		.reg_src = { .reg = S5P_CLKSRC_PERIL0, .shift = 4, .size = 4 },

		.reg_div = { .reg = S5P_CLKDIV_PERIL0, .shift = 4, .size = 4 },

	}, {

		.clk		= {

			.name		= "uclk1",

			.devname	= "s5pv210-uart.2",

			.enable		= exynos4_clksrc_mask_peril0_ctrl,

			.ctrlbit	= (1 << 8),

		},

		.sources = &clkset_group,

		.reg_src = { .reg = S5P_CLKSRC_PERIL0, .shift = 8, .size = 4 },

		.reg_div = { .reg = S5P_CLKDIV_PERIL0, .shift = 8, .size = 4 },

	}, {

		.clk		= {

			.name		= "uclk1",

			.devname	= "s5pv210-uart.3",

			.enable		= exynos4_clksrc_mask_peril0_ctrl,

			.ctrlbit	= (1 << 12),

		},

		.sources = &clkset_group,

		.reg_src = { .reg = S5P_CLKSRC_PERIL0, .shift = 12, .size = 4 },

		.reg_div = { .reg = S5P_CLKDIV_PERIL0, .shift = 12, .size = 4 },

	}, {

		.clk		= {

		.clk		= {

			.name		= "sclk_pwm",

			.name		= "sclk_pwm",

			.enable		= exynos4_clksrc_mask_peril0_ctrl,

			.enable		= exynos4_clksrc_mask_peril0_ctrl,
@@ -1237,6 +1197,54 @@ static struct clksrc_clk clksrcs[] = { 
	}

	}

};

};





static struct clksrc_clk clk_sclk_uart0 = {

	.clk	= {

		.name		= "uclk1",

		.devname	= "exynos4210-uart.0",

		.enable		= exynos4_clksrc_mask_peril0_ctrl,

		.ctrlbit	= (1 << 0),

	},

	.sources = &clkset_group,

	.reg_src = { .reg = S5P_CLKSRC_PERIL0, .shift = 0, .size = 4 },

	.reg_div = { .reg = S5P_CLKDIV_PERIL0, .shift = 0, .size = 4 },

};



static struct clksrc_clk clk_sclk_uart1 = {

	.clk		= {

		.name		= "uclk1",

		.devname	= "exynos4210-uart.1",

		.enable		= exynos4_clksrc_mask_peril0_ctrl,

		.ctrlbit	= (1 << 4),

	},

	.sources = &clkset_group,

	.reg_src = { .reg = S5P_CLKSRC_PERIL0, .shift = 4, .size = 4 },

	.reg_div = { .reg = S5P_CLKDIV_PERIL0, .shift = 4, .size = 4 },

};



static struct clksrc_clk clk_sclk_uart2 = {

	.clk		= {

		.name		= "uclk1",

		.devname	= "exynos4210-uart.2",

		.enable		= exynos4_clksrc_mask_peril0_ctrl,

		.ctrlbit	= (1 << 8),

	},

	.sources = &clkset_group,

	.reg_src = { .reg = S5P_CLKSRC_PERIL0, .shift = 8, .size = 4 },

	.reg_div = { .reg = S5P_CLKDIV_PERIL0, .shift = 8, .size = 4 },

};



static struct clksrc_clk clk_sclk_uart3 = {

	.clk		= {

		.name		= "uclk1",

		.devname	= "exynos4210-uart.3",

		.enable		= exynos4_clksrc_mask_peril0_ctrl,

		.ctrlbit	= (1 << 12),

	},

	.sources = &clkset_group,

	.reg_src = { .reg = S5P_CLKSRC_PERIL0, .shift = 12, .size = 4 },

	.reg_div = { .reg = S5P_CLKDIV_PERIL0, .shift = 12, .size = 4 },

};



/* Clock initialization code */

/* Clock initialization code */

static struct clksrc_clk *sysclks[] = {

static struct clksrc_clk *sysclks[] = {

	&clk_mout_apll,

	&clk_mout_apll,
@@ -1271,6 +1279,20 @@ static struct clksrc_clk *sysclks[] = { 
	&clk_mout_mfc1,

	&clk_mout_mfc1,

};

};





static struct clksrc_clk *clksrc_cdev[] = {

	&clk_sclk_uart0,

	&clk_sclk_uart1,

	&clk_sclk_uart2,

	&clk_sclk_uart3,

};



static struct clk_lookup exynos4_clk_lookup[] = {

	CLKDEV_INIT("exynos4210-uart.0", "clk_uart_baud0", &clk_sclk_uart0.clk),

	CLKDEV_INIT("exynos4210-uart.1", "clk_uart_baud0", &clk_sclk_uart1.clk),

	CLKDEV_INIT("exynos4210-uart.2", "clk_uart_baud0", &clk_sclk_uart2.clk),

	CLKDEV_INIT("exynos4210-uart.3", "clk_uart_baud0", &clk_sclk_uart3.clk),

};



static int xtal_rate;

static int xtal_rate;





static unsigned long exynos4_fout_apll_get_rate(struct clk *clk)

static unsigned long exynos4_fout_apll_get_rate(struct clk *clk)
@@ -1478,11 +1500,15 @@ void __init exynos4_register_clocks(void) 
	for (ptr = 0; ptr < ARRAY_SIZE(sclk_tv); ptr++)

	for (ptr = 0; ptr < ARRAY_SIZE(sclk_tv); ptr++)

		s3c_register_clksrc(sclk_tv[ptr], 1);

		s3c_register_clksrc(sclk_tv[ptr], 1);





	for (ptr = 0; ptr < ARRAY_SIZE(clksrc_cdev); ptr++)

		s3c_register_clksrc(clksrc_cdev[ptr], 1);



	s3c_register_clksrc(clksrcs, ARRAY_SIZE(clksrcs));

	s3c_register_clksrc(clksrcs, ARRAY_SIZE(clksrcs));

	s3c_register_clocks(init_clocks, ARRAY_SIZE(init_clocks));

	s3c_register_clocks(init_clocks, ARRAY_SIZE(init_clocks));





	s3c_register_clocks(init_clocks_off, ARRAY_SIZE(init_clocks_off));

	s3c_register_clocks(init_clocks_off, ARRAY_SIZE(init_clocks_off));

	s3c_disable_clocks(init_clocks_off, ARRAY_SIZE(init_clocks_off));

	s3c_disable_clocks(init_clocks_off, ARRAY_SIZE(init_clocks_off));

	clkdev_add_table(exynos4_clk_lookup, ARRAY_SIZE(exynos4_clk_lookup));





	register_syscore_ops(&exynos4_clock_syscore_ops);

	register_syscore_ops(&exynos4_clock_syscore_ops);

	s3c24xx_register_clock(&dummy_apb_pclk);

	s3c24xx_register_clock(&dummy_apb_pclk);

arch/arm/mach-exynos/init.c

+1 −1
Original line number Original line Diff line number Diff line
@@ -23,5 +23,5 @@ void __init exynos4_common_init_uarts(struct s3c2410_uartcfg *cfg, int no) 
	for (ucnt = 0; ucnt < no; ucnt++, tcfg++)

	for (ucnt = 0; ucnt < no; ucnt++, tcfg++)

		tcfg->has_fracval = 1;

		tcfg->has_fracval = 1;





	s3c24xx_init_uartdevs("s5pv210-uart", s5p_uart_resources, cfg, no);

	s3c24xx_init_uartdevs("exynos4210-uart", s5p_uart_resources, cfg, no);

}
 
}

arch/arm/mach-s3c2410/s3c2410.c

+6 −0
Original line number Original line Diff line number Diff line
@@ -123,12 +123,18 @@ static struct clk s3c2410_armclk = { 
	.id	= -1,

	.id	= -1,

};

};





static struct clk_lookup s3c2410_clk_lookup[] = {

	CLKDEV_INIT(NULL, "clk_uart_baud0", &clk_p),

	CLKDEV_INIT(NULL, "clk_uart_baud1", &s3c24xx_uclk),

};



void __init s3c2410_init_clocks(int xtal)

void __init s3c2410_init_clocks(int xtal)

{

{

	s3c24xx_register_baseclocks(xtal);

	s3c24xx_register_baseclocks(xtal);

	s3c2410_setup_clocks();

	s3c2410_setup_clocks();

	s3c2410_baseclk_add();

	s3c2410_baseclk_add();

	s3c24xx_register_clock(&s3c2410_armclk);

	s3c24xx_register_clock(&s3c2410_armclk);

	clkdev_add_table(s3c2410_clk_lookup, ARRAY_SIZE(s3c2410_clk_lookup));

}

}





struct sysdev_class s3c2410_sysclass = {

struct sysdev_class s3c2410_sysclass = {

arch/arm/mach-s3c2412/clock.c

+7 −0
Original line number Original line Diff line number Diff line
@@ -659,6 +659,12 @@ static struct clk *clks[] __initdata = { 
	&clk_armclk,

	&clk_armclk,

};

};





static struct clk_lookup s3c2412_clk_lookup[] = {

	CLKDEV_INIT(NULL, "clk_uart_baud1", &s3c24xx_uclk),

	CLKDEV_INIT(NULL, "clk_uart_baud2", &clk_p),

	CLKDEV_INIT(NULL, "clk_uart_baud3", &clk_usysclk),

};



int __init s3c2412_baseclk_add(void)

int __init s3c2412_baseclk_add(void)

{

{

	unsigned long clkcon  = __raw_readl(S3C2410_CLKCON);

	unsigned long clkcon  = __raw_readl(S3C2410_CLKCON);
@@ -751,6 +757,7 @@ int __init s3c2412_baseclk_add(void) 
		s3c2412_clkcon_enable(clkp, 0);

		s3c2412_clkcon_enable(clkp, 0);

	}

	}





	clkdev_add_table(s3c2412_clk_lookup, ARRAY_SIZE(s3c2412_clk_lookup));

	s3c_pwmclk_init();

	s3c_pwmclk_init();

	return 0;

	return 0;

}
 
}

arch/arm/mach-s3c2440/clock.c

+7 −0
Original line number Original line Diff line number Diff line
@@ -144,6 +144,12 @@ static struct clk s3c2440_clk_fclk_n = { 
	},

	},

};

};





static struct clk_lookup s3c2440_clk_lookup[] = {

	CLKDEV_INIT(NULL, "clk_uart_baud1", &s3c24xx_uclk),

	CLKDEV_INIT(NULL, "clk_uart_baud2", &clk_p),

	CLKDEV_INIT(NULL, "clk_uart_baud3", &s3c2440_clk_fclk_n),

};



static int s3c2440_clk_add(struct sys_device *sysdev)

static int s3c2440_clk_add(struct sys_device *sysdev)

{

{

	struct clk *clock_upll;

	struct clk *clock_upll;
@@ -167,6 +173,7 @@ static int s3c2440_clk_add(struct sys_device *sysdev) 
	s3c24xx_register_clock(&s3c2440_clk_ac97);

	s3c24xx_register_clock(&s3c2440_clk_ac97);

	s3c24xx_register_clock(&s3c2440_clk_cam);

	s3c24xx_register_clock(&s3c2440_clk_cam);

	s3c24xx_register_clock(&s3c2440_clk_cam_upll);

	s3c24xx_register_clock(&s3c2440_clk_cam_upll);

	clkdev_add_table(s3c2440_clk_lookup, ARRAY_SIZE(s3c2440_clk_lookup));





	clk_disable(&s3c2440_clk_ac97);

	clk_disable(&s3c2440_clk_ac97);

	clk_disable(&s3c2440_clk_cam);

	clk_disable(&s3c2440_clk_cam);