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Commit 0be035f3 authored by Feng Tang's avatar Feng Tang Committed by Dan Williams
Browse files

intel_mid_dma: add support for single item scatter-gather list 



Current driver's device_prep_slave_sg can't be used by DMAC2 even
the sg list contains one item, this patch will enable DMAC2 to
use this API.

Signed-off-by: default avatarFeng Tang <feng.tang@intel.com>
Acked-by: default avatarVinod Koul <vinod.koul@intel.com>
Signed-off-by: default avatarDan Williams <dan.j.williams@intel.com>
parent 66bde0b7

drivers/dma/intel_mid_dma.c

+24 −4
Original line number Original line Diff line number Diff line
@@ -664,11 +664,20 @@ static struct dma_async_tx_descriptor *intel_mid_dma_prep_memcpy( 
	/*calculate CTL_LO*/

	/*calculate CTL_LO*/

	ctl_lo.ctl_lo = 0;

	ctl_lo.ctl_lo = 0;

	ctl_lo.ctlx.int_en = 1;

	ctl_lo.ctlx.int_en = 1;

	ctl_lo.ctlx.dst_tr_width = mids->dma_slave.dst_addr_width;

	ctl_lo.ctlx.src_tr_width = mids->dma_slave.src_addr_width;

	ctl_lo.ctlx.dst_msize = mids->dma_slave.src_maxburst;

	ctl_lo.ctlx.dst_msize = mids->dma_slave.src_maxburst;

	ctl_lo.ctlx.src_msize = mids->dma_slave.dst_maxburst;

	ctl_lo.ctlx.src_msize = mids->dma_slave.dst_maxburst;





	/*

	 * Here we need some translation from "enum dma_slave_buswidth"

	 * to the format for our dma controller

	 *		standard	intel_mid_dmac's format

	 *		 1 Byte			0b000

	 *		 2 Bytes		0b001

	 *		 4 Bytes		0b010

	 */

	ctl_lo.ctlx.dst_tr_width = mids->dma_slave.dst_addr_width / 2;

	ctl_lo.ctlx.src_tr_width = mids->dma_slave.src_addr_width / 2;



	if (mids->cfg_mode == LNW_DMA_MEM_TO_MEM) {

	if (mids->cfg_mode == LNW_DMA_MEM_TO_MEM) {

		ctl_lo.ctlx.tt_fc = 0;

		ctl_lo.ctlx.tt_fc = 0;

		ctl_lo.ctlx.sinc = 0;

		ctl_lo.ctlx.sinc = 0;
@@ -746,9 +755,19 @@ static struct dma_async_tx_descriptor *intel_mid_dma_prep_slave_sg( 
	BUG_ON(!mids);

	BUG_ON(!mids);





	if (!midc->dma->pimr_mask) {

	if (!midc->dma->pimr_mask) {

		pr_debug("MDMA: SG list is not supported by this controller\n");

		/* We can still handle sg list with only one item */

		if (sg_len == 1) {

			txd = intel_mid_dma_prep_memcpy(chan,

						mids->dma_slave.dst_addr,

						mids->dma_slave.src_addr,

						sgl->length,

						flags);

			return txd;

		} else {

			pr_warn("MDMA: SG list is not supported by this controller\n");

			return  NULL;

			return  NULL;

		}

		}

	}





	pr_debug("MDMA: SG Length = %d, direction = %d, Flags = %#lx\n",

	pr_debug("MDMA: SG Length = %d, direction = %d, Flags = %#lx\n",

			sg_len, direction, flags);

			sg_len, direction, flags);
@@ -758,6 +777,7 @@ static struct dma_async_tx_descriptor *intel_mid_dma_prep_slave_sg( 
		pr_err("MDMA: Prep memcpy failed\n");

		pr_err("MDMA: Prep memcpy failed\n");

		return NULL;

		return NULL;

	}

	}



	desc = to_intel_mid_dma_desc(txd);

	desc = to_intel_mid_dma_desc(txd);

	desc->dirn = direction;

	desc->dirn = direction;

	ctl_lo.ctl_lo = desc->ctl_lo;

	ctl_lo.ctl_lo = desc->ctl_lo;