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Commit 08b5b2f7 authored by Bjorn Helgaas's avatar Bjorn Helgaas
Browse files

Merge branch 'pci/aspm' 

  - disable ASPM L1.2 substate if we don't have LTR (Bjorn Helgaas)

  - respect platform ownership of LTR (Bjorn Helgaas)

* pci/aspm:
  PCI/ACPI: Request LTR control from platform before using it
  PCI/ASPM: Disable ASPM L1.2 Substate if we don't have LTR
parents d7e02c08 af8bb9f8

drivers/acpi/pci_root.c

+6 −0
Original line number Diff line number Diff line
@@ -153,6 +153,7 @@ static struct pci_osc_bit_struct pci_osc_control_bit[] = { 
	{ OSC_PCI_EXPRESS_PME_CONTROL, "PME" },

	{ OSC_PCI_EXPRESS_AER_CONTROL, "AER" },

	{ OSC_PCI_EXPRESS_CAPABILITY_CONTROL, "PCIeCapability" },

	{ OSC_PCI_EXPRESS_LTR_CONTROL, "LTR" },

};



static void decode_osc_bits(struct acpi_pci_root *root, char *msg, u32 word,
@@ -475,6 +476,9 @@ static void negotiate_os_control(struct acpi_pci_root *root, int *no_aspm) 
		| OSC_PCI_EXPRESS_NATIVE_HP_CONTROL

		| OSC_PCI_EXPRESS_PME_CONTROL;



	if (IS_ENABLED(CONFIG_PCIEASPM))

		control |= OSC_PCI_EXPRESS_LTR_CONTROL;



	if (pci_aer_available()) {

		if (aer_acpi_firmware_first())

			dev_info(&device->dev,
@@ -905,6 +909,8 @@ struct pci_bus *acpi_pci_root_create(struct acpi_pci_root *root, 
		host_bridge->native_aer = 0;

	if (!(root->osc_control_set & OSC_PCI_EXPRESS_PME_CONTROL))

		host_bridge->native_pme = 0;

	if (!(root->osc_control_set & OSC_PCI_EXPRESS_LTR_CONTROL))

		host_bridge->native_ltr = 0;



	pci_scan_child_bus(bus);

	pci_set_host_bridge_release(host_bridge, acpi_pci_root_release_info,

drivers/pci/pcie/aspm.c

+9 −0
Original line number Diff line number Diff line
@@ -400,6 +400,15 @@ static void pcie_get_aspm_reg(struct pci_dev *pdev, 
		info->l1ss_cap = 0;

		return;

	}



	/*

	 * If we don't have LTR for the entire path from the Root Complex

	 * to this device, we can't use ASPM L1.2 because it relies on the

	 * LTR_L1.2_THRESHOLD.  See PCIe r4.0, secs 5.5.4, 6.18.

	 */

	if (!pdev->ltr_path)

		info->l1ss_cap &= ~PCI_L1SS_CAP_ASPM_L1_2;



	pci_read_config_dword(pdev, info->l1ss_cap_ptr + PCI_L1SS_CTL1,

			      &info->l1ss_ctl1);

	pci_read_config_dword(pdev, info->l1ss_cap_ptr + PCI_L1SS_CTL2,

drivers/pci/probe.c

+5 −0
Original line number Diff line number Diff line
@@ -554,6 +554,7 @@ struct pci_host_bridge *pci_alloc_host_bridge(size_t priv) 
	bridge->native_aer = 1;

	bridge->native_hotplug = 1;

	bridge->native_pme = 1;

	bridge->native_ltr = 1;



	return bridge;

}
@@ -1954,9 +1955,13 @@ static void pci_configure_relaxed_ordering(struct pci_dev *dev) 
static void pci_configure_ltr(struct pci_dev *dev)

{

#ifdef CONFIG_PCIEASPM

	struct pci_host_bridge *host = pci_find_host_bridge(dev->bus);

	u32 cap;

	struct pci_dev *bridge;



	if (!host->native_ltr)

		return;



	if (!pci_is_pcie(dev))

		return;

include/linux/acpi.h

+2 −1
Original line number Diff line number Diff line
@@ -506,7 +506,8 @@ extern bool osc_pc_lpi_support_confirmed; 
#define OSC_PCI_EXPRESS_PME_CONTROL		0x00000004

#define OSC_PCI_EXPRESS_AER_CONTROL		0x00000008

#define OSC_PCI_EXPRESS_CAPABILITY_CONTROL	0x00000010

#define OSC_PCI_CONTROL_MASKS			0x0000001f

#define OSC_PCI_EXPRESS_LTR_CONTROL		0x00000020

#define OSC_PCI_CONTROL_MASKS			0x0000003f



#define ACPI_GSB_ACCESS_ATTRIB_QUICK		0x00000002

#define ACPI_GSB_ACCESS_ATTRIB_SEND_RCV         0x00000004

include/linux/pci.h

+1 −0
Original line number Diff line number Diff line
@@ -473,6 +473,7 @@ struct pci_host_bridge { 
	unsigned int	native_aer:1;		/* OS may use PCIe AER */

	unsigned int	native_hotplug:1;	/* OS may use PCIe hotplug */

	unsigned int	native_pme:1;		/* OS may use PCIe PME */

	unsigned int	native_ltr:1;		/* OS may use PCIe LTR */

	/* Resource alignment requirements */

	resource_size_t (*align_resource)(struct pci_dev *dev,

			const struct resource *res,