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Commit 0883b4f4 authored by Gal Pressman's avatar Gal Pressman Committed by Saeed Mahameed
Browse files

net/mlx5e: Reduce number of heap allocated buffers for update stats 



Allocating buffers on the heap every 200ms is something we should avoid,
let's use buffers located on the stack instead.

Signed-off-by: default avatarGal Pressman <galp@mellanox.com>
Reviewed-by: default avatarEran Ben Elisha <eranbe@mellanox.com>
Signed-off-by: default avatarSaeed Mahameed <saeedm@mellanox.com>
Cc: kernel-team@fb.com
parent ebc88870

drivers/net/ethernet/mellanox/mlx5/core/en_main.c

+2 −14
Original line number Original line Diff line number Diff line
@@ -248,14 +248,10 @@ static void mlx5e_update_pport_counters(struct mlx5e_priv *priv) 
{

{

	struct mlx5e_pport_stats *pstats = &priv->stats.pport;

	struct mlx5e_pport_stats *pstats = &priv->stats.pport;

	struct mlx5_core_dev *mdev = priv->mdev;

	struct mlx5_core_dev *mdev = priv->mdev;

	u32 in[MLX5_ST_SZ_DW(ppcnt_reg)] = {0};

	int sz = MLX5_ST_SZ_BYTES(ppcnt_reg);

	int sz = MLX5_ST_SZ_BYTES(ppcnt_reg);

	int prio;

	int prio;

	void *out;

	void *out;

	u32 *in;



	in = kvzalloc(sz, GFP_KERNEL);

	if (!in)

		return;





	MLX5_SET(ppcnt_reg, in, local_port, 1);

	MLX5_SET(ppcnt_reg, in, local_port, 1);
@@ -288,8 +284,6 @@ static void mlx5e_update_pport_counters(struct mlx5e_priv *priv) 
		mlx5_core_access_reg(mdev, in, sz, out, sz,

		mlx5_core_access_reg(mdev, in, sz, out, sz,

				     MLX5_REG_PPCNT, 0, 0);

				     MLX5_REG_PPCNT, 0, 0);

	}

	}



	kvfree(in);

}

}





static void mlx5e_update_q_counter(struct mlx5e_priv *priv)

static void mlx5e_update_q_counter(struct mlx5e_priv *priv)
@@ -307,22 +301,16 @@ static void mlx5e_update_pcie_counters(struct mlx5e_priv *priv) 
{

{

	struct mlx5e_pcie_stats *pcie_stats = &priv->stats.pcie;

	struct mlx5e_pcie_stats *pcie_stats = &priv->stats.pcie;

	struct mlx5_core_dev *mdev = priv->mdev;

	struct mlx5_core_dev *mdev = priv->mdev;

	u32 in[MLX5_ST_SZ_DW(mpcnt_reg)] = {0};

	int sz = MLX5_ST_SZ_BYTES(mpcnt_reg);

	int sz = MLX5_ST_SZ_BYTES(mpcnt_reg);

	void *out;

	void *out;

	u32 *in;





	if (!MLX5_CAP_MCAM_FEATURE(mdev, pcie_performance_group))

	if (!MLX5_CAP_MCAM_FEATURE(mdev, pcie_performance_group))

		return;

		return;





	in = kvzalloc(sz, GFP_KERNEL);

	if (!in)

		return;



	out = pcie_stats->pcie_perf_counters;

	out = pcie_stats->pcie_perf_counters;

	MLX5_SET(mpcnt_reg, in, grp, MLX5_PCIE_PERFORMANCE_COUNTERS_GROUP);

	MLX5_SET(mpcnt_reg, in, grp, MLX5_PCIE_PERFORMANCE_COUNTERS_GROUP);

	mlx5_core_access_reg(mdev, in, sz, out, sz, MLX5_REG_MPCNT, 0, 0);

	mlx5_core_access_reg(mdev, in, sz, out, sz, MLX5_REG_MPCNT, 0, 0);



	kvfree(in);

}

}





void mlx5e_update_stats(struct mlx5e_priv *priv)

void mlx5e_update_stats(struct mlx5e_priv *priv)