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Commit 057b670d authored by Olof Johansson's avatar Olof Johansson
Browse files

Merge tag 'renesas-dt-for-v4.8' of... 

Merge tag 'renesas-dt-for-v4.8' of git://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas into next/dt

Renesas ARM Based SoC DT Updates for v4.8

* Fix W=1 dtc warnings
* Reverence both DMA controllers on R-Car Gen 2 SoCs
* Remove nonexistent thermal sensor clock from r8a7794 SoC
* Correct unit names for cpu nodes on r8a7790 SoC
* Add MMCIF0 to r8a7793 SoC
* RTS/CTS hardware flow control for kzm9g and bockw boards

* tag 'renesas-dt-for-v4.8' of git://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas

: (30 commits)
  ARM: dts: silk: Fix W=1 dtc warnings
  ARM: dts: porter: Fix W=1 dtc warnings
  ARM: dts: marzen: Fix W=1 dtc warnings
  ARM: dts: lager: Fix W=1 dtc warnings
  ARM: dts: kzm9g: Fix W=1 dtc warnings
  ARM: dts: kzm9d: Fix W=1 dtc warnings
  ARM: dts: koelsch: Fix W=1 dtc warnings
  ARM: dts: gose: Fix W=1 dtc warnings
  ARM: dts: genmai: Fix W=1 dtc warnings
  ARM: dts: bockw: Fix W=1 dtc warnings
  ARM: dts: armadillo800eva: Fix W=1 dtc warnings
  ARM: dts: ape6evm: Fix W=1 dtc warnings
  ARM: dts: sh73a0: Fix W=1 dtc warnings
  ARM: dts: r8a7794: Fix W=1 dtc warnings
  ARM: dts: r8a7793: Fix W=1 dtc warnings
  ARM: dts: r8a7791: Fix W=1 dtc warnings
  ARM: dts: r8a7790: Fix W=1 dtc warnings
  ARM: dts: r8a7778: Fix W=1 dtc warnings
  ARM: dts: r8a7740: Fix W=1 dtc warnings
  ARM: dts: r8a73a4: Fix W=1 dtc warnings
  ...

Signed-off-by: default avatarOlof Johansson <olof@lixom.net>
parents 95eb940c b6960f19

arch/arm/boot/dts/emev2-kzm9d.dts

+8 −8
Original line number Diff line number Diff line
@@ -18,7 +18,7 @@ 
	model = "EMEV2 KZM9D Board";

	compatible = "renesas,kzm9d", "renesas,emev2";



	memory {

	memory@40000000 {

		device_type = "memory";

		reg = <0x40000000 0x8000000>;

	};
@@ -33,28 +33,28 @@ 
		#address-cells = <1>;

		#size-cells = <0>;



		button@1 {

		one {

			debounce_interval = <50>;

			wakeup-source;

			label = "DSW2-1";

			linux,code = <KEY_1>;

			gpios = <&gpio0 14 GPIO_ACTIVE_HIGH>;

		};

		button@2 {

		two {

			debounce_interval = <50>;

			wakeup-source;

			label = "DSW2-2";

			linux,code = <KEY_2>;

			gpios = <&gpio0 15 GPIO_ACTIVE_HIGH>;

		};

		button@3 {

		three {

			debounce_interval = <50>;

			wakeup-source;

			label = "DSW2-3";

			linux,code = <KEY_3>;

			gpios = <&gpio0 16 GPIO_ACTIVE_HIGH>;

		};

		button@4 {

		four {

			debounce_interval = <50>;

			wakeup-source;

			label = "DSW2-4";
@@ -63,7 +63,7 @@ 
		};

	};



	reg_1p8v: regulator@0 {

	reg_1p8v: regulator-1p8v {

		compatible = "regulator-fixed";

		regulator-name = "fixed-1.8V";

		regulator-min-microvolt = <1800000>;
@@ -72,7 +72,7 @@ 
		regulator-boot-on;

	};



	reg_3p3v: regulator@1 {

	reg_3p3v: regulator-3p3v {

		compatible = "regulator-fixed";

		regulator-name = "fixed-3.3V";

		regulator-min-microvolt = <3300000>;
@@ -104,7 +104,7 @@ 
};



&pfc {

	uart1_pins: serial@e1030000 {

	uart1_pins: uart1 {

		groups = "uart1_ctrl", "uart1_data";

		function = "uart1";

	};

arch/arm/boot/dts/emev2.dtsi

+13 −13
Original line number Diff line number Diff line
@@ -69,25 +69,25 @@ 
			clock-frequency = <32768>;

			#clock-cells = <0>;

		};

		iic0_sclkdiv: iic0_sclkdiv {

		iic0_sclkdiv: iic0_sclkdiv@624,0 {

			compatible = "renesas,emev2-smu-clkdiv";

			reg = <0x624 0>;

			clocks = <&pll3_fo>;

			#clock-cells = <0>;

		};

		iic0_sclk: iic0_sclk {

		iic0_sclk: iic0_sclk@48c,1 {

			compatible = "renesas,emev2-smu-gclk";

			reg = <0x48c 1>;

			clocks = <&iic0_sclkdiv>;

			#clock-cells = <0>;

		};

		iic1_sclkdiv: iic1_sclkdiv {

		iic1_sclkdiv: iic1_sclkdiv@624,16 {

			compatible = "renesas,emev2-smu-clkdiv";

			reg = <0x624 16>;

			clocks = <&pll3_fo>;

			#clock-cells = <0>;

		};

		iic1_sclk: iic1_sclk {

		iic1_sclk: iic1_sclk@490,1 {

			compatible = "renesas,emev2-smu-gclk";

			reg = <0x490 1>;

			clocks = <&iic1_sclkdiv>;
@@ -100,55 +100,55 @@ 
			clock-mult = <7000>;

			#clock-cells = <0>;

		};

		usia_u0_sclkdiv: usia_u0_sclkdiv {

		usia_u0_sclkdiv: usia_u0_sclkdiv@610,0 {

			compatible = "renesas,emev2-smu-clkdiv";

			reg = <0x610 0>;

			clocks = <&pll3_fo>;

			#clock-cells = <0>;

		};

		usib_u1_sclkdiv: usib_u1_sclkdiv {

		usib_u1_sclkdiv: usib_u1_sclkdiv@65c,0 {

			compatible = "renesas,emev2-smu-clkdiv";

			reg = <0x65c 0>;

			clocks = <&pll3_fo>;

			#clock-cells = <0>;

		};

		usib_u2_sclkdiv: usib_u2_sclkdiv {

		usib_u2_sclkdiv: usib_u2_sclkdiv@65c,16 {

			compatible = "renesas,emev2-smu-clkdiv";

			reg = <0x65c 16>;

			clocks = <&pll3_fo>;

			#clock-cells = <0>;

		};

		usib_u3_sclkdiv: usib_u3_sclkdiv {

		usib_u3_sclkdiv: usib_u3_sclkdiv@660,0 {

			compatible = "renesas,emev2-smu-clkdiv";

			reg = <0x660 0>;

			clocks = <&pll3_fo>;

			#clock-cells = <0>;

		};

		usia_u0_sclk: usia_u0_sclk {

		usia_u0_sclk: usia_u0_sclk@4a0,1 {

			compatible = "renesas,emev2-smu-gclk";

			reg = <0x4a0 1>;

			clocks = <&usia_u0_sclkdiv>;

			#clock-cells = <0>;

		};

		usib_u1_sclk: usib_u1_sclk {

		usib_u1_sclk: usib_u1_sclk@4b8,1 {

			compatible = "renesas,emev2-smu-gclk";

			reg = <0x4b8 1>;

			clocks = <&usib_u1_sclkdiv>;

			#clock-cells = <0>;

		};

		usib_u2_sclk: usib_u2_sclk {

		usib_u2_sclk: usib_u2_sclk@4bc,1 {

			compatible = "renesas,emev2-smu-gclk";

			reg = <0x4bc 1>;

			clocks = <&usib_u2_sclkdiv>;

			#clock-cells = <0>;

		};

		usib_u3_sclk: usib_u3_sclk {

		usib_u3_sclk: usib_u3_sclk@4c0,1 {

			compatible = "renesas,emev2-smu-gclk";

			reg = <0x4c0 1>;

			clocks = <&usib_u3_sclkdiv>;

			#clock-cells = <0>;

		};

		sti_sclk: sti_sclk {

		sti_sclk: sti_sclk@528,1 {

			compatible = "renesas,emev2-smu-gclk";

			reg = <0x528 1>;

			clocks = <&c32ki>;

arch/arm/boot/dts/r7s72100-genmai.dts

+1 −1
Original line number Diff line number Diff line
@@ -25,7 +25,7 @@ 
		stdout-path = &scif2;

	};



	memory {

	memory@8000000 {

		device_type = "memory";

		reg = <0x08000000 0x08000000>;

	};

arch/arm/boot/dts/r8a73a4-ape6evm.dts

+4 −4
Original line number Diff line number Diff line
@@ -36,7 +36,7 @@ 
		reg = <2 0x00000000 0 0x40000000>;

	};



	vcc_mmc0: regulator@0 {

	vcc_mmc0: regulator-mmc0 {

		compatible = "regulator-fixed";

		regulator-name = "MMC0 Vcc";

		regulator-min-microvolt = <2800000>;
@@ -44,7 +44,7 @@ 
		regulator-always-on;

	};



	vcc_sdhi0: regulator@1 {

	vcc_sdhi0: regulator-sdhi0 {

		compatible = "regulator-fixed";



		regulator-name = "SDHI0 Vcc";
@@ -56,7 +56,7 @@ 
	};



	/* Common 1.8V and 3.3V rails, used by several devices on APE6EVM */

	ape6evm_fixed_1v8: regulator@2 {

	ape6evm_fixed_1v8: regulator-1v8 {

		compatible = "regulator-fixed";

		regulator-name = "1V8";

		regulator-min-microvolt = <1800000>;
@@ -64,7 +64,7 @@ 
		regulator-always-on;

	};



	ape6evm_fixed_3v3: regulator@3 {

	ape6evm_fixed_3v3: regulator-3v3 {

		compatible = "regulator-fixed";

		regulator-name = "3V3";

		regulator-min-microvolt = <3300000>;

arch/arm/boot/dts/r8a73a4.dtsi

+18 −16
Original line number Diff line number Diff line
@@ -31,36 +31,38 @@ 
			power-domains = <&pd_a2sl>;

			next-level-cache = <&L2_CA15>;

		};

	};



	ptm {

		compatible = "arm,coresight-etm3x";

		power-domains = <&pd_d4>;

	};



	timer {

		compatible = "arm,armv7-timer";

		interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,

			     <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,

			     <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,

			     <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;

	};



		L2_CA15: cache-controller@0 {

			compatible = "cache";

			reg = <0>;

			clocks = <&cpg_clocks R8A73A4_CLK_Z>;

			power-domains = <&pd_a3sm>;

			cache-unified;

			cache-level = <2>;

		};



	L2_CA7: cache-controller@1 {

		L2_CA7: cache-controller@100 {

			compatible = "cache";

			reg = <0x100>;

			clocks = <&cpg_clocks R8A73A4_CLK_Z2>;

			power-domains = <&pd_a3km>;

			cache-unified;

			cache-level = <2>;

		};

	};



	ptm {

		compatible = "arm,coresight-etm3x";

		power-domains = <&pd_d4>;

	};



	timer {

		compatible = "arm,armv7-timer";

		interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,

			     <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,

			     <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,

			     <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;

	};



	dbsc1: memory-controller@e6790000 {

		compatible = "renesas,dbsc-r8a73a4";