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Commit 04606ccc authored by Luis Oliveira's avatar Luis Oliveira Committed by Wolfram Sang
Browse files

i2c: designware: introducing I2C_SLAVE definitions 



- Definitions were added to core library
- A example was added to designware-core.txt Documentation that shows
  how the slave can be setup using DTS

SLAVE related definitions were added to the core of the controller.

Signed-off-by: default avatarLuis Oliveira <lolivei@synopsys.com>
Reviewed-by: default avatarAndy Shevchenko <andriy.shevchenko@linux.intel.com>
Acked-by: default avatarRob Herring <robh@kernel.org>
Acked-by: default avatarJarkko Nikula <jarkko.nikula@linux.intel.com>
Signed-off-by: default avatarWolfram Sang <wsa@the-dreams.de>
parent 90312351

Documentation/devicetree/bindings/i2c/i2c-designware.txt

+15 −1
Original line number Diff line number Diff line
@@ -20,7 +20,7 @@ Optional properties : 
 - i2c-sda-falling-time-ns : should contain the SDA falling time in nanoseconds.

   This value which is by default 300ns is used to compute the tHIGH period.



Example :

Examples :



	i2c@f0000 {

		#address-cells = <1>;
@@ -43,3 +43,17 @@ Example : 
		i2c-sda-falling-time-ns = <300>;

		i2c-scl-falling-time-ns = <300>;

	};



	i2c@1120000 {

		#address-cells = <1>;

		#size-cells = <0>;

		reg = <0x2000 0x100>;

		clock-frequency = <400000>;

		clocks = <&i2cclk>;

		interrupts = <0>;



		eeprom@64 {

			compatible = "linux,slave-24c02";

			reg = <0x40000064>;

		};

	};

drivers/i2c/busses/i2c-designware-core.h

+31 −2
Original line number Diff line number Diff line 
/*

 * Synopsys DesignWare I2C adapter driver (master only).

 * Synopsys DesignWare I2C adapter driver.

 *

 * Based on the TI DAVINCI I2C adapter driver.

 *
@@ -37,15 +37,20 @@ 
#define DW_IC_CON_SPEED_FAST		0x4

#define DW_IC_CON_SPEED_HIGH		0x6

#define DW_IC_CON_SPEED_MASK		0x6

#define DW_IC_CON_10BITADDR_SLAVE		0x8

#define DW_IC_CON_10BITADDR_MASTER	0x10

#define DW_IC_CON_RESTART_EN		0x20

#define DW_IC_CON_SLAVE_DISABLE		0x40

#define DW_IC_CON_STOP_DET_IFADDRESSED		0x80

#define DW_IC_CON_TX_EMPTY_CTRL		0x100

#define DW_IC_CON_RX_FIFO_FULL_HLD_CTRL		0x200



/*

 * Registers offset

 */

#define DW_IC_CON		0x0

#define DW_IC_TAR		0x4

#define DW_IC_SAR		0x8

#define DW_IC_DATA_CMD		0x10

#define DW_IC_SS_SCL_HCNT	0x14

#define DW_IC_SS_SCL_LCNT	0x18
@@ -76,6 +81,7 @@ 
#define DW_IC_SDA_HOLD		0x7c

#define DW_IC_TX_ABRT_SOURCE	0x80

#define DW_IC_ENABLE_STATUS	0x9c

#define DW_IC_CLR_RESTART_DET	0xa8

#define DW_IC_COMP_PARAM_1	0xf4

#define DW_IC_COMP_VERSION	0xf8

#define DW_IC_SDA_HOLD_MIN_VERS	0x3131312A
@@ -94,15 +100,22 @@ 
#define DW_IC_INTR_STOP_DET	0x200

#define DW_IC_INTR_START_DET	0x400

#define DW_IC_INTR_GEN_CALL	0x800

#define DW_IC_INTR_RESTART_DET	0x1000



#define DW_IC_INTR_DEFAULT_MASK		(DW_IC_INTR_RX_FULL | \

					 DW_IC_INTR_TX_ABRT | \

					 DW_IC_INTR_STOP_DET)

#define DW_IC_INTR_MASTER_MASK		(DW_IC_INTR_DEFAULT_MASK | \

					 DW_IC_INTR_TX_EMPTY)

#define DW_IC_INTR_SLAVE_MASK		(DW_IC_INTR_DEFAULT_MASK | \

					 DW_IC_INTR_RX_DONE | \

					 DW_IC_INTR_RX_UNDER | \

					 DW_IC_INTR_RD_REQ)



#define DW_IC_STATUS_ACTIVITY		0x1

#define DW_IC_STATUS_TFE		BIT(2)

#define DW_IC_STATUS_MASTER_ACTIVITY	BIT(5)

#define DW_IC_STATUS_SLAVE_ACTIVITY	BIT(6)



#define DW_IC_SDA_HOLD_RX_SHIFT		16

#define DW_IC_SDA_HOLD_RX_MASK		GENMASK(23, DW_IC_SDA_HOLD_RX_SHIFT)
@@ -115,7 +128,7 @@ 
#define DW_IC_COMP_PARAM_1_SPEED_MODE_MASK	GENMASK(3, 2)



/*

 * Status codes

 * status codes

 */

#define STATUS_IDLE			0x0

#define STATUS_WRITE_IN_PROGRESS	0x1
@@ -123,6 +136,12 @@ 


#define TIMEOUT			20 /* ms */



/*

 * operation modes

 */

#define DW_IC_MASTER		0

#define DW_IC_SLAVE		1



/*

 * Hardware abort codes from the DW_IC_TX_ABRT_SOURCE register

 *
@@ -140,6 +159,9 @@ 
#define ABRT_10B_RD_NORSTRT	10

#define ABRT_MASTER_DIS		11

#define ARB_LOST		12

#define ABRT_SLAVE_FLUSH_TXFIFO	13

#define ABRT_SLAVE_ARBLOST	14

#define ABRT_SLAVE_RD_INTX	15



#define DW_IC_TX_ABRT_7B_ADDR_NOACK	(1UL << ABRT_7B_ADDR_NOACK)

#define DW_IC_TX_ABRT_10ADDR1_NOACK	(1UL << ABRT_10ADDR1_NOACK)
@@ -152,6 +174,9 @@ 
#define DW_IC_TX_ABRT_10B_RD_NORSTRT	(1UL << ABRT_10B_RD_NORSTRT)

#define DW_IC_TX_ABRT_MASTER_DIS	(1UL << ABRT_MASTER_DIS)

#define DW_IC_TX_ARB_LOST		(1UL << ARB_LOST)

#define DW_IC_RX_ABRT_SLAVE_RD_INTX	(1UL << ABRT_SLAVE_RD_INTX)

#define DW_IC_RX_ABRT_SLAVE_ARBLOST	(1UL << ABRT_SLAVE_ARBLOST)

#define DW_IC_RX_ABRT_SLAVE_FLUSH_TXFIFO	(1UL << ABRT_SLAVE_FLUSH_TXFIFO)



#define DW_IC_TX_ABRT_NOACK		(DW_IC_TX_ABRT_7B_ADDR_NOACK | \

					 DW_IC_TX_ABRT_10ADDR1_NOACK | \
@@ -166,6 +191,7 @@ 
 * @base: IO registers pointer

 * @cmd_complete: tx completion indicator

 * @clk: input reference clock

 * @slave: represent an I2C slave device

 * @cmd_err: run time hadware error code

 * @msgs: points to an array of messages currently being transferred

 * @msgs_num: the number of elements in msgs
@@ -182,6 +208,7 @@ 
 * @abort_source: copy of the TX_ABRT_SOURCE register

 * @irq: interrupt number for the i2c master

 * @adapter: i2c subsystem adapter node

 * @slave_cfg: configuration for the slave device

 * @tx_fifo_depth: depth of the hardware tx fifo

 * @rx_fifo_depth: depth of the hardware rx fifo

 * @rx_outstanding: current master-rx elements in tx fifo
@@ -212,6 +239,7 @@ struct dw_i2c_dev { 
	struct completion	cmd_complete;

	struct clk		*clk;

	struct reset_control	*rst;

	struct i2c_client		*slave;

	u32			(*get_clk_rate_khz) (struct dw_i2c_dev *dev);

	struct dw_pci_controller *controller;

	int			cmd_err;
@@ -231,6 +259,7 @@ struct dw_i2c_dev { 
	struct i2c_adapter	adapter;

	u32			functionality;

	u32			master_cfg;

	u32			slave_cfg;

	unsigned int		tx_fifo_depth;

	unsigned int		rx_fifo_depth;

	int			rx_outstanding;