MIPS: Reorganize Cavium OCTEON PCI support. (01a6221a) · Commits · e / devices / android_kernel_teracube_mt6765

arch/mips/cavium-octeon/Makefile

+0 −4

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	@@ -14,9 +14,5 @@ obj-y += dma-octeon.o flash_setup.o
	obj-y += octeon-memcpy.o		obj-y += octeon-memcpy.o

	obj-$(CONFIG_SMP) += smp.o		obj-$(CONFIG_SMP) += smp.o
	obj-$(CONFIG_PCI) += pci-common.o
	obj-$(CONFIG_PCI) += pci.o
	obj-$(CONFIG_PCI) += pcie.o
	obj-$(CONFIG_PCI_MSI) += msi.o

	EXTRA_CFLAGS += -Werror		EXTRA_CFLAGS += -Werror

arch/mips/cavium-octeon/dma-octeon.c

+1 −1

Original line number	Original line	Diff line number	Diff line
	@@ -29,7 +29,7 @@
	#include <dma-coherence.h>		#include <dma-coherence.h>

	#ifdef CONFIG_PCI		#ifdef CONFIG_PCI
	#include "pci-common.h"		#include <asm/octeon/pci-octeon.h>
	#endif		#endif

	#define BAR2_PCI_ADDRESS 0x8000000000ul		#define BAR2_PCI_ADDRESS 0x8000000000ul

arch/mips/cavium-octeon/pci-common.c

deleted100644 → 0

+0 −137

Original line number	Original line	Diff line number	Diff line
	/*
	* This file is subject to the terms and conditions of the GNU General Public
	* License. See the file "COPYING" in the main directory of this archive
	* for more details.
	*
	* Copyright (C) 2005-2007 Cavium Networks
	*/
	#include <linux/kernel.h>
	#include <linux/init.h>
	#include <linux/pci.h>
	#include <linux/interrupt.h>
	#include <linux/time.h>
	#include <linux/delay.h>
	#include "pci-common.h"

	typeof(pcibios_map_irq) *octeon_pcibios_map_irq;
	enum octeon_dma_bar_type octeon_dma_bar_type = OCTEON_DMA_BAR_TYPE_INVALID;

	/**
	* Map a PCI device to the appropriate interrupt line
	*
	* @param dev The Linux PCI device structure for the device to map
	* @param slot The slot number for this device on __BUS 0__. Linux
	* enumerates through all the bridges and figures out the
	* slot on Bus 0 where this device eventually hooks to.
	* @param pin The PCI interrupt pin read from the device, then swizzled
	* as it goes through each bridge.
	* @return Interrupt number for the device
	*/
	int __init pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
	{
	if (octeon_pcibios_map_irq)
	return octeon_pcibios_map_irq(dev, slot, pin);
	else
	panic("octeon_pcibios_map_irq doesn't point to a "
	"pcibios_map_irq() function");
	}


	/**
	* Called to perform platform specific PCI setup
	*
	* @param dev
	* @return
	*/
	int pcibios_plat_dev_init(struct pci_dev *dev)
	{
	uint16_t config;
	uint32_t dconfig;
	int pos;
	/*
	* Force the Cache line setting to 64 bytes. The standard
	* Linux bus scan doesn't seem to set it. Octeon really has
	* 128 byte lines, but Intel bridges get really upset if you
	* try and set values above 64 bytes. Value is specified in
	* 32bit words.
	*/
	pci_write_config_byte(dev, PCI_CACHE_LINE_SIZE, 64 / 4);
	/* Set latency timers for all devices */
	pci_write_config_byte(dev, PCI_LATENCY_TIMER, 48);

	/* Enable reporting System errors and parity errors on all devices */
	/* Enable parity checking and error reporting */
	pci_read_config_word(dev, PCI_COMMAND, &config);
	config \|= PCI_COMMAND_PARITY \| PCI_COMMAND_SERR;
	pci_write_config_word(dev, PCI_COMMAND, config);

	if (dev->subordinate) {
	/* Set latency timers on sub bridges */
	pci_write_config_byte(dev, PCI_SEC_LATENCY_TIMER, 48);
	/* More bridge error detection */
	pci_read_config_word(dev, PCI_BRIDGE_CONTROL, &config);
	config \|= PCI_BRIDGE_CTL_PARITY \| PCI_BRIDGE_CTL_SERR;
	pci_write_config_word(dev, PCI_BRIDGE_CONTROL, config);
	}

	/* Enable the PCIe normal error reporting */
	pos = pci_find_capability(dev, PCI_CAP_ID_EXP);
	if (pos) {
	/* Update Device Control */
	pci_read_config_word(dev, pos + PCI_EXP_DEVCTL, &config);
	/* Correctable Error Reporting */
	config \|= PCI_EXP_DEVCTL_CERE;
	/* Non-Fatal Error Reporting */
	config \|= PCI_EXP_DEVCTL_NFERE;
	/* Fatal Error Reporting */
	config \|= PCI_EXP_DEVCTL_FERE;
	/* Unsupported Request */
	config \|= PCI_EXP_DEVCTL_URRE;
	pci_write_config_word(dev, pos + PCI_EXP_DEVCTL, config);
	}

	/* Find the Advanced Error Reporting capability */
	pos = pci_find_ext_capability(dev, PCI_EXT_CAP_ID_ERR);
	if (pos) {
	/* Clear Uncorrectable Error Status */
	pci_read_config_dword(dev, pos + PCI_ERR_UNCOR_STATUS,
	&dconfig);
	pci_write_config_dword(dev, pos + PCI_ERR_UNCOR_STATUS,
	dconfig);
	/* Enable reporting of all uncorrectable errors */
	/* Uncorrectable Error Mask - turned on bits disable errors */
	pci_write_config_dword(dev, pos + PCI_ERR_UNCOR_MASK, 0);
	/*
	* Leave severity at HW default. This only controls if
	* errors are reported as uncorrectable or
	* correctable, not if the error is reported.
	*/
	/* PCI_ERR_UNCOR_SEVER - Uncorrectable Error Severity */
	/* Clear Correctable Error Status */
	pci_read_config_dword(dev, pos + PCI_ERR_COR_STATUS, &dconfig);
	pci_write_config_dword(dev, pos + PCI_ERR_COR_STATUS, dconfig);
	/* Enable reporting of all correctable errors */
	/* Correctable Error Mask - turned on bits disable errors */
	pci_write_config_dword(dev, pos + PCI_ERR_COR_MASK, 0);
	/* Advanced Error Capabilities */
	pci_read_config_dword(dev, pos + PCI_ERR_CAP, &dconfig);
	/* ECRC Generation Enable */
	if (config & PCI_ERR_CAP_ECRC_GENC)
	config \|= PCI_ERR_CAP_ECRC_GENE;
	/* ECRC Check Enable */
	if (config & PCI_ERR_CAP_ECRC_CHKC)
	config \|= PCI_ERR_CAP_ECRC_CHKE;
	pci_write_config_dword(dev, pos + PCI_ERR_CAP, dconfig);
	/* PCI_ERR_HEADER_LOG - Header Log Register (16 bytes) */
	/* Report all errors to the root complex */
	pci_write_config_dword(dev, pos + PCI_ERR_ROOT_COMMAND,
	PCI_ERR_ROOT_CMD_COR_EN \|
	PCI_ERR_ROOT_CMD_NONFATAL_EN \|
	PCI_ERR_ROOT_CMD_FATAL_EN);
	/* Clear the Root status register */
	pci_read_config_dword(dev, pos + PCI_ERR_ROOT_STATUS, &dconfig);
	pci_write_config_dword(dev, pos + PCI_ERR_ROOT_STATUS, dconfig);
	}

	return 0;
	}

arch/mips/cavium-octeon/pci-common.h→arch/mips/include/asm/octeon/pci-octeon.h

+18 −12

Original line number	Original line	Diff line number	Diff line
	@@ -3,23 +3,29 @@
	* License. See the file "COPYING" in the main directory of this archive		* License. See the file "COPYING" in the main directory of this archive
	* for more details.		* for more details.
	*		*
	* Copyright (C) 2005-2007 Cavium Networks		* Copyright (C) 2005-2009 Cavium Networks
	*/		*/
	#ifndef __OCTEON_PCI_COMMON_H__
	#define __OCTEON_PCI_COMMON_H__		#ifndef __PCI_OCTEON_H__
			#define __PCI_OCTEON_H__

	#include <linux/pci.h>		#include <linux/pci.h>

	/* Some PCI cards require delays when accessing config space. */		/* Some PCI cards require delays when accessing config space. */
	#define PCI_CONFIG_SPACE_DELAY 10000		#define PCI_CONFIG_SPACE_DELAY 10000

	/* pcibios_map_irq() is defined inside pci-common.c. All it does is call the		/*
	Octeon specific version pointed to by this variable. This function needs to		* pcibios_map_irq() is defined inside pci-octeon.c. All it does is
	change for PCI or PCIe based hosts */		* call the Octeon specific version pointed to by this variable. This
	extern typeof(pcibios_map_irq) *octeon_pcibios_map_irq;		* function needs to change for PCI or PCIe based hosts.
			*/
			extern int (octeon_pcibios_map_irq)(const struct pci_dev dev,
			u8 slot, u8 pin);

	/* The following defines are only used when octeon_dma_bar_type =		/*
	OCTEON_DMA_BAR_TYPE_BIG */		* The following defines are used when octeon_dma_bar_type =
			* OCTEON_DMA_BAR_TYPE_BIG
			*/
	#define OCTEON_PCI_BAR1_HOLE_BITS 5		#define OCTEON_PCI_BAR1_HOLE_BITS 5
	#define OCTEON_PCI_BAR1_HOLE_SIZE (1ul<<(OCTEON_PCI_BAR1_HOLE_BITS+3))		#define OCTEON_PCI_BAR1_HOLE_SIZE (1ul<<(OCTEON_PCI_BAR1_HOLE_BITS+3))

	@@ -30,9 +36,9 @@ enum octeon_dma_bar_type {
	OCTEON_DMA_BAR_TYPE_PCIE		OCTEON_DMA_BAR_TYPE_PCIE
	};		};

	/**		/*
	* This is a variable to tell the DMA mapping system in dma-octeon.c		* This tells the DMA mapping system in dma-octeon.c how to map PCI
	* how to map PCI DMA addresses.		* DMA addresses.
	*/		*/
	extern enum octeon_dma_bar_type octeon_dma_bar_type;		extern enum octeon_dma_bar_type octeon_dma_bar_type;

arch/mips/pci/Makefile

+5 −0

Original line number	Original line	Diff line number	Diff line
	@@ -52,3 +52,8 @@ obj-$(CONFIG_VICTOR_MPC30X) += fixup-mpc30x.o
	obj-$(CONFIG_ZAO_CAPCELLA) += fixup-capcella.o		obj-$(CONFIG_ZAO_CAPCELLA) += fixup-capcella.o
	obj-$(CONFIG_WR_PPMC) += fixup-wrppmc.o		obj-$(CONFIG_WR_PPMC) += fixup-wrppmc.o
	obj-$(CONFIG_MIKROTIK_RB532) += pci-rc32434.o ops-rc32434.o fixup-rc32434.o		obj-$(CONFIG_MIKROTIK_RB532) += pci-rc32434.o ops-rc32434.o fixup-rc32434.o
			obj-$(CONFIG_CPU_CAVIUM_OCTEON) += pci-octeon.o pcie-octeon.o

			ifdef CONFIG_PCI_MSI
			obj-$(CONFIG_CPU_CAVIUM_OCTEON) += msi-octeon.o
			endif