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Commit ff49fad1 authored by Jay Agarwal's avatar Jay Agarwal Committed by Mike Turquette
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ARM: tegra30: clocks: Fix pciex clock registration 



Registering pciex as peripheral clock instead of fixed clock
as tegra_perih_reset_assert(deassert) api of this clock api
gives warning and ultimately does not succeed to assert(deassert)

Signed-off-by: default avatarJay Agarwal <jagarwal@nvidia.com>
Acked-by: default avatarStephen Warren <swarren@nvidia.com>
Signed-off-by: default avatarMike Turquette <mturquette@linaro.org>
parent 346f372f

drivers/clk/tegra/clk-tegra30.c

+6 −5
Original line number Diff line number Diff line
@@ -1598,6 +1598,12 @@ static void __init tegra30_periph_clk_init(void) 
	clk_register_clkdev(clk, "afi", "tegra-pcie");

	clks[afi] = clk;



	/* pciex */

	clk = tegra_clk_register_periph_gate("pciex", "pll_e", 0, clk_base, 0,

				    74, &periph_u_regs, periph_clk_enb_refcnt);

	clk_register_clkdev(clk, "pciex", "tegra-pcie");

	clks[pciex] = clk;



	/* kfuse */

	clk = tegra_clk_register_periph_gate("kfuse", "clk_m",

				    TEGRA_PERIPH_ON_APB,
@@ -1716,11 +1722,6 @@ static void __init tegra30_fixed_clk_init(void) 
				1, 0, &cml_lock);

	clk_register_clkdev(clk, "cml1", NULL);

	clks[cml1] = clk;



	/* pciex */

	clk = clk_register_fixed_rate(NULL, "pciex", "pll_e", 0, 100000000);

	clk_register_clkdev(clk, "pciex", NULL);

	clks[pciex] = clk;

}



static void __init tegra30_osc_clk_init(void)