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Commit fe68e68f authored by Catalin Marinas's avatar Catalin Marinas Committed by Russell King
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[ARM] 5439/1: Do not clear bit 10 of DFSR during abort handling on ARMv6 



Because of an ARM1136 erratum (326103), the current v6_early_abort
function needs to set the correct FSR[11] value which determines whether
the data abort was caused by a read or write. For legacy reasons (bit 10
not handled by software), bit 10 was also cleared masking out imprecise
aborts on ARMv6 CPUs. This patch removes the clearing of bit 10 of FSR.

Signed-off-by: default avatarCatalin Marinas <catalin.marinas@arm.com>
Signed-off-by: default avatarRussell King <rmk+kernel@arm.linux.org.uk>
parent 01a24d2b

arch/arm/mm/abort-ev6.S

+2 −2
Original line number Original line Diff line number Diff line
@@ -29,10 +29,10 @@ ENTRY(v6_early_abort) 
	mrc	p15, 0, r1, c5, c0, 0		@ get FSR

	mrc	p15, 0, r1, c5, c0, 0		@ get FSR

	mrc	p15, 0, r0, c6, c0, 0		@ get FAR

	mrc	p15, 0, r0, c6, c0, 0		@ get FAR

/*

/*

 * Faulty SWP instruction on 1136 doesn't set bit 11 in DFSR.

 * Faulty SWP instruction on 1136 doesn't set bit 11 in DFSR (erratum 326103).

 * The test below covers all the write situations, including Java bytecodes

 * The test below covers all the write situations, including Java bytecodes

 */

 */

	bic	r1, r1, #1 << 11 | 1 << 10	@ clear bits 11 and 10 of FSR

	bic	r1, r1, #1 << 11		@ clear bit 11 of FSR

	tst	r3, #PSR_J_BIT			@ Java?

	tst	r3, #PSR_J_BIT			@ Java?

	movne	pc, lr

	movne	pc, lr

	do_thumb_abort

	do_thumb_abort