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Commit fe5a4901 authored by Hema HK's avatar Hema HK Committed by Felipe Balbi
Browse files

usb: musb: AM35x: moving internal phy functions out of usb_musb.c file 



Moved all the board specific internal PHY functions out of usb_musb.c file
as this file is shared between the OMAP2+ and AM35xx platforms.
There exists a file which has the functions specific to internal PHY
used for OMAP4 platform. Moved all phy specific functions to this file
and passing these functions through board data in the board file.

Signed-off-by: default avatarHema HK <hemahk@ti.com>
Cc: Paul Walmsley <paul@pwsan.com>
Cc: Tony Lindgren <tony@atomide.com>
Signed-off-by: default avatarFelipe Balbi <balbi@ti.com>
parent 85e2efbb

arch/arm/mach-omap2/Makefile

+2 −1
Original line number Diff line number Diff line
@@ -218,7 +218,8 @@ obj-$(CONFIG_MACH_OMAP4_PANDA) += board-omap4panda.o \ 
					   hsmmc.o \

					   omap_phy_internal.o



obj-$(CONFIG_MACH_OMAP3517EVM)		+= board-am3517evm.o

obj-$(CONFIG_MACH_OMAP3517EVM)		+= board-am3517evm.o \

					   omap_phy_internal.o \



obj-$(CONFIG_MACH_CRANEBOARD)		+= board-am3517crane.o

arch/arm/mach-omap2/board-am3517evm.c

+4 −0
Original line number Diff line number Diff line
@@ -409,6 +409,10 @@ static struct omap_musb_board_data musb_board_data = { 
	.interface_type         = MUSB_INTERFACE_ULPI,

	.mode                   = MUSB_OTG,

	.power                  = 500,

	.set_phy_power		= am35x_musb_phy_power,

	.clear_irq		= am35x_musb_clear_irq,

	.set_mode		= am35x_musb_set_mode,

	.reset			= am35x_musb_reset,

};



static __init void am3517_evm_musb_init(void)

arch/arm/mach-omap2/omap_phy_internal.c

+93 −0
Original line number Diff line number Diff line
@@ -29,6 +29,7 @@ 
#include <linux/usb.h>



#include <plat/usb.h>

#include "control.h"



/* OMAP control module register for UTMI PHY */

#define CONTROL_DEV_CONF		0x300
@@ -147,3 +148,95 @@ int omap4430_phy_exit(struct device *dev) 


	return 0;

}



void am35x_musb_reset(void)

{

	u32	regval;



	/* Reset the musb interface */

	regval = omap_ctrl_readl(AM35XX_CONTROL_IP_SW_RESET);



	regval |= AM35XX_USBOTGSS_SW_RST;

	omap_ctrl_writel(regval, AM35XX_CONTROL_IP_SW_RESET);



	regval &= ~AM35XX_USBOTGSS_SW_RST;

	omap_ctrl_writel(regval, AM35XX_CONTROL_IP_SW_RESET);



	regval = omap_ctrl_readl(AM35XX_CONTROL_IP_SW_RESET);

}



void am35x_musb_phy_power(u8 on)

{

	unsigned long timeout = jiffies + msecs_to_jiffies(100);

	u32 devconf2;



	if (on) {

		/*

		 * Start the on-chip PHY and its PLL.

		 */

		devconf2 = omap_ctrl_readl(AM35XX_CONTROL_DEVCONF2);



		devconf2 &= ~(CONF2_RESET | CONF2_PHYPWRDN | CONF2_OTGPWRDN);

		devconf2 |= CONF2_PHY_PLLON;



		omap_ctrl_writel(devconf2, AM35XX_CONTROL_DEVCONF2);



		pr_info(KERN_INFO "Waiting for PHY clock good...\n");

		while (!(omap_ctrl_readl(AM35XX_CONTROL_DEVCONF2)

				& CONF2_PHYCLKGD)) {

			cpu_relax();



			if (time_after(jiffies, timeout)) {

				pr_err(KERN_ERR "musb PHY clock good timed out\n");

				break;

			}

		}

	} else {

		/*

		 * Power down the on-chip PHY.

		 */

		devconf2 = omap_ctrl_readl(AM35XX_CONTROL_DEVCONF2);



		devconf2 &= ~CONF2_PHY_PLLON;

		devconf2 |=  CONF2_PHYPWRDN | CONF2_OTGPWRDN;

		omap_ctrl_writel(devconf2, AM35XX_CONTROL_DEVCONF2);

	}

}



void am35x_musb_clear_irq(void)

{

	u32 regval;



	regval = omap_ctrl_readl(AM35XX_CONTROL_LVL_INTR_CLEAR);

	regval |= AM35XX_USBOTGSS_INT_CLR;

	omap_ctrl_writel(regval, AM35XX_CONTROL_LVL_INTR_CLEAR);

	regval = omap_ctrl_readl(AM35XX_CONTROL_LVL_INTR_CLEAR);

}



void am35x_musb_set_mode(u8 musb_mode)

{

	u32 devconf2 = omap_ctrl_readl(AM35XX_CONTROL_DEVCONF2);



	devconf2 &= ~CONF2_OTGMODE;

	switch (musb_mode) {

#ifdef	CONFIG_USB_MUSB_HDRC_HCD

	case MUSB_HOST:		/* Force VBUS valid, ID = 0 */

		devconf2 |= CONF2_FORCE_HOST;

		break;

#endif

#ifdef	CONFIG_USB_GADGET_MUSB_HDRC

	case MUSB_PERIPHERAL:	/* Force VBUS valid, ID = 1 */

		devconf2 |= CONF2_FORCE_DEVICE;

		break;

#endif

#ifdef	CONFIG_USB_MUSB_OTG

	case MUSB_OTG:		/* Don't override the VBUS/ID comparators */

		devconf2 |= CONF2_NO_OVERRIDE;

		break;

#endif

	default:

		pr_info(KERN_INFO "Unsupported mode %u\n", musb_mode);

	}



	omap_ctrl_writel(devconf2, AM35XX_CONTROL_DEVCONF2);

}

arch/arm/mach-omap2/usb-musb.c

+0 −97
Original line number Diff line number Diff line
@@ -30,102 +30,9 @@ 
#include <mach/irqs.h>

#include <mach/am35xx.h>

#include <plat/usb.h>

#include "control.h"



#if defined(CONFIG_USB_MUSB_OMAP2PLUS) || defined (CONFIG_USB_MUSB_AM35X)



static void am35x_musb_reset(void)

{

	u32	regval;



	/* Reset the musb interface */

	regval = omap_ctrl_readl(AM35XX_CONTROL_IP_SW_RESET);



	regval |= AM35XX_USBOTGSS_SW_RST;

	omap_ctrl_writel(regval, AM35XX_CONTROL_IP_SW_RESET);



	regval &= ~AM35XX_USBOTGSS_SW_RST;

	omap_ctrl_writel(regval, AM35XX_CONTROL_IP_SW_RESET);



	regval = omap_ctrl_readl(AM35XX_CONTROL_IP_SW_RESET);

}



static void am35x_musb_phy_power(u8 on)

{

	unsigned long timeout = jiffies + msecs_to_jiffies(100);

	u32 devconf2;



	if (on) {

		/*

		 * Start the on-chip PHY and its PLL.

		 */

		devconf2 = omap_ctrl_readl(AM35XX_CONTROL_DEVCONF2);



		devconf2 &= ~(CONF2_RESET | CONF2_PHYPWRDN | CONF2_OTGPWRDN);

		devconf2 |= CONF2_PHY_PLLON;



		omap_ctrl_writel(devconf2, AM35XX_CONTROL_DEVCONF2);



		pr_info(KERN_INFO "Waiting for PHY clock good...\n");

		while (!(omap_ctrl_readl(AM35XX_CONTROL_DEVCONF2)

				& CONF2_PHYCLKGD)) {

			cpu_relax();



			if (time_after(jiffies, timeout)) {

				pr_err(KERN_ERR "musb PHY clock good timed out\n");

				break;

			}

		}

	} else {

		/*

		 * Power down the on-chip PHY.

		 */

		devconf2 = omap_ctrl_readl(AM35XX_CONTROL_DEVCONF2);



		devconf2 &= ~CONF2_PHY_PLLON;

		devconf2 |=  CONF2_PHYPWRDN | CONF2_OTGPWRDN;

		omap_ctrl_writel(devconf2, AM35XX_CONTROL_DEVCONF2);

	}

}



static void am35x_musb_clear_irq(void)

{

	u32 regval;



	regval = omap_ctrl_readl(AM35XX_CONTROL_LVL_INTR_CLEAR);

	regval |= AM35XX_USBOTGSS_INT_CLR;

	omap_ctrl_writel(regval, AM35XX_CONTROL_LVL_INTR_CLEAR);

	regval = omap_ctrl_readl(AM35XX_CONTROL_LVL_INTR_CLEAR);

}



static void am35x_musb_set_mode(u8 musb_mode)

{

	u32 devconf2 = omap_ctrl_readl(AM35XX_CONTROL_DEVCONF2);



	devconf2 &= ~CONF2_OTGMODE;

	switch (musb_mode) {

#ifdef	CONFIG_USB_MUSB_HDRC_HCD

	case MUSB_HOST:		/* Force VBUS valid, ID = 0 */

		devconf2 |= CONF2_FORCE_HOST;

		break;

#endif

#ifdef	CONFIG_USB_GADGET_MUSB_HDRC

	case MUSB_PERIPHERAL:	/* Force VBUS valid, ID = 1 */

		devconf2 |= CONF2_FORCE_DEVICE;

		break;

#endif

#ifdef	CONFIG_USB_MUSB_OTG

	case MUSB_OTG:		/* Don't override the VBUS/ID comparators */

		devconf2 |= CONF2_NO_OVERRIDE;

		break;

#endif

	default:

		pr_info(KERN_INFO "Unsupported mode %u\n", musb_mode);

	}



	omap_ctrl_writel(devconf2, AM35XX_CONTROL_DEVCONF2);

}



static struct resource musb_resources[] = {

	[0] = { /* start and end set dynamically */

		.flags	= IORESOURCE_MEM,
@@ -189,10 +96,6 @@ void __init usb_musb_init(struct omap_musb_board_data *board_data) 
		musb_device.name = "musb-am35x";

		musb_resources[0].start = AM35XX_IPSS_USBOTGSS_BASE;

		musb_resources[1].start = INT_35XX_USBOTG_IRQ;

		board_data->set_phy_power = am35x_musb_phy_power;

		board_data->clear_irq = am35x_musb_clear_irq;

		board_data->set_mode = am35x_musb_set_mode;

		board_data->reset = am35x_musb_reset;

	} else if (cpu_is_omap34xx()) {

		musb_resources[0].start = OMAP34XX_HSUSB_OTG_BASE;

	} else if (cpu_is_omap44xx()) {

arch/arm/plat-omap/include/plat/usb.h

+4 −0
Original line number Diff line number Diff line
@@ -91,6 +91,10 @@ extern int omap4430_phy_exit(struct device *dev); 


#endif



extern void am35x_musb_reset(void);

extern void am35x_musb_phy_power(u8 on);

extern void am35x_musb_clear_irq(void);

extern void am35x_musb_set_mode(u8 musb_mode);



/*

 * FIXME correct answer depends on hmc_mode,