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Commit fd716fca authored by James Hogan's avatar James Hogan Committed by Ralf Baechle
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MIPS: perf: Fix I6400 event numbers 



Fix perf hardware performance counter event numbers for I6400. This core
does not follow the performance event numbering scheme of previous MIPS
cores. All performance counters (both odd and even) are capable of
counting any of the available events.

Fixes: 4e88a862 ("MIPS: Add cases for CPU_I6400")
Signed-off-by: default avatarJames Hogan <james.hogan@imgtec.com>
Cc: Peter Zijlstra <peterz@infradead.org>
Cc: Ingo Molnar <mingo@redhat.com>
Cc: Arnaldo Carvalho de Melo <acme@kernel.org>
Cc: Alexander Shishkin <alexander.shishkin@linux.intel.com>
Cc: linux-mips@linux-mips.org
Cc: linux-kernel@vger.kernel.org
Patchwork: https://patchwork.linux-mips.org/patch/13259/


Signed-off-by: default avatarRalf Baechle <ralf@linux-mips.org>
parent e48b4dac

arch/mips/kernel/perf_event_mipsxx.c

+52 −2
Original line number Diff line number Diff line
@@ -823,6 +823,16 @@ static const struct mips_perf_event mipsxxcore_event_map2 
	[PERF_COUNT_HW_BRANCH_MISSES] = { 0x27, CNTR_ODD, T },

};



static const struct mips_perf_event i6400_event_map[PERF_COUNT_HW_MAX] = {

	[PERF_COUNT_HW_CPU_CYCLES]          = { 0x00, CNTR_EVEN | CNTR_ODD },

	[PERF_COUNT_HW_INSTRUCTIONS]        = { 0x01, CNTR_EVEN | CNTR_ODD },

	/* These only count dcache, not icache */

	[PERF_COUNT_HW_CACHE_REFERENCES]    = { 0x45, CNTR_EVEN | CNTR_ODD },

	[PERF_COUNT_HW_CACHE_MISSES]        = { 0x48, CNTR_EVEN | CNTR_ODD },

	[PERF_COUNT_HW_BRANCH_INSTRUCTIONS] = { 0x15, CNTR_EVEN | CNTR_ODD },

	[PERF_COUNT_HW_BRANCH_MISSES]       = { 0x16, CNTR_EVEN | CNTR_ODD },

};



static const struct mips_perf_event loongson3_event_map[PERF_COUNT_HW_MAX] = {

	[PERF_COUNT_HW_CPU_CYCLES] = { 0x00, CNTR_EVEN },

	[PERF_COUNT_HW_INSTRUCTIONS] = { 0x00, CNTR_ODD },
@@ -1013,6 +1023,46 @@ static const struct mips_perf_event mipsxxcore_cache_map2 
},

};



static const struct mips_perf_event i6400_cache_map

				[PERF_COUNT_HW_CACHE_MAX]

				[PERF_COUNT_HW_CACHE_OP_MAX]

				[PERF_COUNT_HW_CACHE_RESULT_MAX] = {

[C(L1D)] = {

	[C(OP_READ)] = {

		[C(RESULT_ACCESS)]	= { 0x46, CNTR_EVEN | CNTR_ODD },

		[C(RESULT_MISS)]	= { 0x49, CNTR_EVEN | CNTR_ODD },

	},

	[C(OP_WRITE)] = {

		[C(RESULT_ACCESS)]	= { 0x47, CNTR_EVEN | CNTR_ODD },

		[C(RESULT_MISS)]	= { 0x4a, CNTR_EVEN | CNTR_ODD },

	},

},

[C(L1I)] = {

	[C(OP_READ)] = {

		[C(RESULT_ACCESS)]	= { 0x84, CNTR_EVEN | CNTR_ODD },

		[C(RESULT_MISS)]	= { 0x85, CNTR_EVEN | CNTR_ODD },

	},

},

[C(DTLB)] = {

	/* Can't distinguish read & write */

	[C(OP_READ)] = {

		[C(RESULT_ACCESS)]	= { 0x40, CNTR_EVEN | CNTR_ODD },

		[C(RESULT_MISS)]	= { 0x41, CNTR_EVEN | CNTR_ODD },

	},

	[C(OP_WRITE)] = {

		[C(RESULT_ACCESS)]	= { 0x40, CNTR_EVEN | CNTR_ODD },

		[C(RESULT_MISS)]	= { 0x41, CNTR_EVEN | CNTR_ODD },

	},

},

[C(BPU)] = {

	/* Conditional branches / mispredicted */

	[C(OP_READ)] = {

		[C(RESULT_ACCESS)]	= { 0x15, CNTR_EVEN | CNTR_ODD },

		[C(RESULT_MISS)]	= { 0x16, CNTR_EVEN | CNTR_ODD },

	},

},

};



static const struct mips_perf_event loongson3_cache_map

				[PERF_COUNT_HW_CACHE_MAX]

				[PERF_COUNT_HW_CACHE_OP_MAX]
@@ -1724,8 +1774,8 @@ init_hw_perf_events(void) 
		break;

	case CPU_I6400:

		mipspmu.name = "mips/I6400";

		mipspmu.general_event_map = &mipsxxcore_event_map2;

		mipspmu.cache_event_map = &mipsxxcore_cache_map2;

		mipspmu.general_event_map = &i6400_event_map;

		mipspmu.cache_event_map = &i6400_cache_map;

		break;

	case CPU_1004K:

		mipspmu.name = "mips/1004K";