Loading Documentation/powerpc/booting-without-of.txt +2 −1166 File changed.Preview size limit exceeded, changes collapsed. Show changes Documentation/powerpc/dts-bindings/4xx/emac.txt 0 → 100644 +148 −0 Original line number Diff line number Diff line 4xx/Axon EMAC ethernet nodes The EMAC ethernet controller in IBM and AMCC 4xx chips, and also the Axon bridge. To operate this needs to interact with a ths special McMAL DMA controller, and sometimes an RGMII or ZMII interface. In addition to the nodes and properties described below, the node for the OPB bus on which the EMAC sits must have a correct clock-frequency property. i) The EMAC node itself Required properties: - device_type : "network" - compatible : compatible list, contains 2 entries, first is "ibm,emac-CHIP" where CHIP is the host ASIC (440gx, 405gp, Axon) and second is either "ibm,emac" or "ibm,emac4". For Axon, thus, we have: "ibm,emac-axon", "ibm,emac4" - interrupts : <interrupt mapping for EMAC IRQ and WOL IRQ> - interrupt-parent : optional, if needed for interrupt mapping - reg : <registers mapping> - local-mac-address : 6 bytes, MAC address - mal-device : phandle of the associated McMAL node - mal-tx-channel : 1 cell, index of the tx channel on McMAL associated with this EMAC - mal-rx-channel : 1 cell, index of the rx channel on McMAL associated with this EMAC - cell-index : 1 cell, hardware index of the EMAC cell on a given ASIC (typically 0x0 and 0x1 for EMAC0 and EMAC1 on each Axon chip) - max-frame-size : 1 cell, maximum frame size supported in bytes - rx-fifo-size : 1 cell, Rx fifo size in bytes for 10 and 100 Mb/sec operations. For Axon, 2048 - tx-fifo-size : 1 cell, Tx fifo size in bytes for 10 and 100 Mb/sec operations. For Axon, 2048. - fifo-entry-size : 1 cell, size of a fifo entry (used to calculate thresholds). For Axon, 0x00000010 - mal-burst-size : 1 cell, MAL burst size (used to calculate thresholds) in bytes. For Axon, 0x00000100 (I think ...) - phy-mode : string, mode of operations of the PHY interface. Supported values are: "mii", "rmii", "smii", "rgmii", "tbi", "gmii", rtbi", "sgmii". For Axon on CAB, it is "rgmii" - mdio-device : 1 cell, required iff using shared MDIO registers (440EP). phandle of the EMAC to use to drive the MDIO lines for the PHY used by this EMAC. - zmii-device : 1 cell, required iff connected to a ZMII. phandle of the ZMII device node - zmii-channel : 1 cell, required iff connected to a ZMII. Which ZMII channel or 0xffffffff if ZMII is only used for MDIO. - rgmii-device : 1 cell, required iff connected to an RGMII. phandle of the RGMII device node. For Axon: phandle of plb5/plb4/opb/rgmii - rgmii-channel : 1 cell, required iff connected to an RGMII. Which RGMII channel is used by this EMAC. Fox Axon: present, whatever value is appropriate for each EMAC, that is the content of the current (bogus) "phy-port" property. Optional properties: - phy-address : 1 cell, optional, MDIO address of the PHY. If absent, a search is performed. - phy-map : 1 cell, optional, bitmap of addresses to probe the PHY for, used if phy-address is absent. bit 0x00000001 is MDIO address 0. For Axon it can be absent, though my current driver doesn't handle phy-address yet so for now, keep 0x00ffffff in it. - rx-fifo-size-gige : 1 cell, Rx fifo size in bytes for 1000 Mb/sec operations (if absent the value is the same as rx-fifo-size). For Axon, either absent or 2048. - tx-fifo-size-gige : 1 cell, Tx fifo size in bytes for 1000 Mb/sec operations (if absent the value is the same as tx-fifo-size). For Axon, either absent or 2048. - tah-device : 1 cell, optional. If connected to a TAH engine for offload, phandle of the TAH device node. - tah-channel : 1 cell, optional. If appropriate, channel used on the TAH engine. Example: EMAC0: ethernet@40000800 { device_type = "network"; compatible = "ibm,emac-440gp", "ibm,emac"; interrupt-parent = <&UIC1>; interrupts = <1c 4 1d 4>; reg = <40000800 70>; local-mac-address = [00 04 AC E3 1B 1E]; mal-device = <&MAL0>; mal-tx-channel = <0 1>; mal-rx-channel = <0>; cell-index = <0>; max-frame-size = <5dc>; rx-fifo-size = <1000>; tx-fifo-size = <800>; phy-mode = "rmii"; phy-map = <00000001>; zmii-device = <&ZMII0>; zmii-channel = <0>; }; ii) McMAL node Required properties: - device_type : "dma-controller" - compatible : compatible list, containing 2 entries, first is "ibm,mcmal-CHIP" where CHIP is the host ASIC (like emac) and the second is either "ibm,mcmal" or "ibm,mcmal2". For Axon, "ibm,mcmal-axon","ibm,mcmal2" - interrupts : <interrupt mapping for the MAL interrupts sources: 5 sources: tx_eob, rx_eob, serr, txde, rxde>. For Axon: This is _different_ from the current firmware. We use the "delayed" interrupts for txeob and rxeob. Thus we end up with mapping those 5 MPIC interrupts, all level positive sensitive: 10, 11, 32, 33, 34 (in decimal) - dcr-reg : < DCR registers range > - dcr-parent : if needed for dcr-reg - num-tx-chans : 1 cell, number of Tx channels - num-rx-chans : 1 cell, number of Rx channels iii) ZMII node Required properties: - compatible : compatible list, containing 2 entries, first is "ibm,zmii-CHIP" where CHIP is the host ASIC (like EMAC) and the second is "ibm,zmii". For Axon, there is no ZMII node. - reg : <registers mapping> iv) RGMII node Required properties: - compatible : compatible list, containing 2 entries, first is "ibm,rgmii-CHIP" where CHIP is the host ASIC (like EMAC) and the second is "ibm,rgmii". For Axon, "ibm,rgmii-axon","ibm,rgmii" - reg : <registers mapping> - revision : as provided by the RGMII new version register if available. For Axon: 0x0000012a Documentation/powerpc/dts-bindings/gpio/gpio.txt 0 → 100644 +50 −0 Original line number Diff line number Diff line Specifying GPIO information for devices ============================================ 1) gpios property ----------------- Nodes that makes use of GPIOs should define them using `gpios' property, format of which is: <&gpio-controller1-phandle gpio1-specifier &gpio-controller2-phandle gpio2-specifier 0 /* holes are permitted, means no GPIO 3 */ &gpio-controller4-phandle gpio4-specifier ...>; Note that gpio-specifier length is controller dependent. gpio-specifier may encode: bank, pin position inside the bank, whether pin is open-drain and whether pin is logically inverted. Example of the node using GPIOs: node { gpios = <&qe_pio_e 18 0>; }; In this example gpio-specifier is "18 0" and encodes GPIO pin number, and empty GPIO flags as accepted by the "qe_pio_e" gpio-controller. 2) gpio-controller nodes ------------------------ Every GPIO controller node must have #gpio-cells property defined, this information will be used to translate gpio-specifiers. Example of two SOC GPIO banks defined as gpio-controller nodes: qe_pio_a: gpio-controller@1400 { #gpio-cells = <2>; compatible = "fsl,qe-pario-bank-a", "fsl,qe-pario-bank"; reg = <0x1400 0x18>; gpio-controller; }; qe_pio_e: gpio-controller@1460 { #gpio-cells = <2>; compatible = "fsl,qe-pario-bank-e", "fsl,qe-pario-bank"; reg = <0x1460 0x18>; gpio-controller; }; Documentation/powerpc/dts-bindings/gpio/mdio.txt 0 → 100644 +19 −0 Original line number Diff line number Diff line MDIO on GPIOs Currently defined compatibles: - virtual,gpio-mdio MDC and MDIO lines connected to GPIO controllers are listed in the gpios property as described in section VIII.1 in the following order: MDC, MDIO. Example: mdio { compatible = "virtual,mdio-gpio"; #address-cells = <1>; #size-cells = <0>; gpios = <&qe_pio_a 11 &qe_pio_c 6>; }; Documentation/powerpc/dts-bindings/marvell.txt 0 → 100644 +521 −0 Original line number Diff line number Diff line Marvell Discovery mv64[345]6x System Controller chips =========================================================== The Marvell mv64[345]60 series of system controller chips contain many of the peripherals needed to implement a complete computer system. In this section, we define device tree nodes to describe the system controller chip itself and each of the peripherals which it contains. Compatible string values for each node are prefixed with the string "marvell,", for Marvell Technology Group Ltd. 1) The /system-controller node This node is used to represent the system-controller and must be present when the system uses a system controller chip. The top-level system-controller node contains information that is global to all devices within the system controller chip. The node name begins with "system-controller" followed by the unit address, which is the base address of the memory-mapped register set for the system controller chip. Required properties: - ranges : Describes the translation of system controller addresses for memory mapped registers. - clock-frequency: Contains the main clock frequency for the system controller chip. - reg : This property defines the address and size of the memory-mapped registers contained within the system controller chip. The address specified in the "reg" property should match the unit address of the system-controller node. - #address-cells : Address representation for system controller devices. This field represents the number of cells needed to represent the address of the memory-mapped registers of devices within the system controller chip. - #size-cells : Size representation for for the memory-mapped registers within the system controller chip. - #interrupt-cells : Defines the width of cells used to represent interrupts. Optional properties: - model : The specific model of the system controller chip. Such as, "mv64360", "mv64460", or "mv64560". - compatible : A string identifying the compatibility identifiers of the system controller chip. The system-controller node contains child nodes for each system controller device that the platform uses. Nodes should not be created for devices which exist on the system controller chip but are not used Example Marvell Discovery mv64360 system-controller node: system-controller@f1000000 { /* Marvell Discovery mv64360 */ #address-cells = <1>; #size-cells = <1>; model = "mv64360"; /* Default */ compatible = "marvell,mv64360"; clock-frequency = <133333333>; reg = <0xf1000000 0x10000>; virtual-reg = <0xf1000000>; ranges = <0x88000000 0x88000000 0x1000000 /* PCI 0 I/O Space */ 0x80000000 0x80000000 0x8000000 /* PCI 0 MEM Space */ 0xa0000000 0xa0000000 0x4000000 /* User FLASH */ 0x00000000 0xf1000000 0x0010000 /* Bridge's regs */ 0xf2000000 0xf2000000 0x0040000>;/* Integrated SRAM */ [ child node definitions... ] } 2) Child nodes of /system-controller a) Marvell Discovery MDIO bus The MDIO is a bus to which the PHY devices are connected. For each device that exists on this bus, a child node should be created. See the definition of the PHY node below for an example of how to define a PHY. Required properties: - #address-cells : Should be <1> - #size-cells : Should be <0> - device_type : Should be "mdio" - compatible : Should be "marvell,mv64360-mdio" Example: mdio { #address-cells = <1>; #size-cells = <0>; device_type = "mdio"; compatible = "marvell,mv64360-mdio"; ethernet-phy@0 { ...... }; }; b) Marvell Discovery ethernet controller The Discover ethernet controller is described with two levels of nodes. The first level describes an ethernet silicon block and the second level describes up to 3 ethernet nodes within that block. The reason for the multiple levels is that the registers for the node are interleaved within a single set of registers. The "ethernet-block" level describes the shared register set, and the "ethernet" nodes describe ethernet port-specific properties. Ethernet block node Required properties: - #address-cells : <1> - #size-cells : <0> - compatible : "marvell,mv64360-eth-block" - reg : Offset and length of the register set for this block Example Discovery Ethernet block node: ethernet-block@2000 { #address-cells = <1>; #size-cells = <0>; compatible = "marvell,mv64360-eth-block"; reg = <0x2000 0x2000>; ethernet@0 { ....... }; }; Ethernet port node Required properties: - device_type : Should be "network". - compatible : Should be "marvell,mv64360-eth". - reg : Should be <0>, <1>, or <2>, according to which registers within the silicon block the device uses. - interrupts : <a> where a is the interrupt number for the port. - interrupt-parent : the phandle for the interrupt controller that services interrupts for this device. - phy : the phandle for the PHY connected to this ethernet controller. - local-mac-address : 6 bytes, MAC address Example Discovery Ethernet port node: ethernet@0 { device_type = "network"; compatible = "marvell,mv64360-eth"; reg = <0>; interrupts = <32>; interrupt-parent = <&PIC>; phy = <&PHY0>; local-mac-address = [ 00 00 00 00 00 00 ]; }; c) Marvell Discovery PHY nodes Required properties: - device_type : Should be "ethernet-phy" - interrupts : <a> where a is the interrupt number for this phy. - interrupt-parent : the phandle for the interrupt controller that services interrupts for this device. - reg : The ID number for the phy, usually a small integer Example Discovery PHY node: ethernet-phy@1 { device_type = "ethernet-phy"; compatible = "broadcom,bcm5421"; interrupts = <76>; /* GPP 12 */ interrupt-parent = <&PIC>; reg = <1>; }; d) Marvell Discovery SDMA nodes Represent DMA hardware associated with the MPSC (multiprotocol serial controllers). Required properties: - compatible : "marvell,mv64360-sdma" - reg : Offset and length of the register set for this device - interrupts : <a> where a is the interrupt number for the DMA device. - interrupt-parent : the phandle for the interrupt controller that services interrupts for this device. Example Discovery SDMA node: sdma@4000 { compatible = "marvell,mv64360-sdma"; reg = <0x4000 0xc18>; virtual-reg = <0xf1004000>; interrupts = <36>; interrupt-parent = <&PIC>; }; e) Marvell Discovery BRG nodes Represent baud rate generator hardware associated with the MPSC (multiprotocol serial controllers). Required properties: - compatible : "marvell,mv64360-brg" - reg : Offset and length of the register set for this device - clock-src : A value from 0 to 15 which selects the clock source for the baud rate generator. This value corresponds to the CLKS value in the BRGx configuration register. See the mv64x60 User's Manual. - clock-frequence : The frequency (in Hz) of the baud rate generator's input clock. - current-speed : The current speed setting (presumably by firmware) of the baud rate generator. Example Discovery BRG node: brg@b200 { compatible = "marvell,mv64360-brg"; reg = <0xb200 0x8>; clock-src = <8>; clock-frequency = <133333333>; current-speed = <9600>; }; f) Marvell Discovery CUNIT nodes Represent the Serial Communications Unit device hardware. Required properties: - reg : Offset and length of the register set for this device Example Discovery CUNIT node: cunit@f200 { reg = <0xf200 0x200>; }; g) Marvell Discovery MPSCROUTING nodes Represent the Discovery's MPSC routing hardware Required properties: - reg : Offset and length of the register set for this device Example Discovery CUNIT node: mpscrouting@b500 { reg = <0xb400 0xc>; }; h) Marvell Discovery MPSCINTR nodes Represent the Discovery's MPSC DMA interrupt hardware registers (SDMA cause and mask registers). Required properties: - reg : Offset and length of the register set for this device Example Discovery MPSCINTR node: mpsintr@b800 { reg = <0xb800 0x100>; }; i) Marvell Discovery MPSC nodes Represent the Discovery's MPSC (Multiprotocol Serial Controller) serial port. Required properties: - device_type : "serial" - compatible : "marvell,mv64360-mpsc" - reg : Offset and length of the register set for this device - sdma : the phandle for the SDMA node used by this port - brg : the phandle for the BRG node used by this port - cunit : the phandle for the CUNIT node used by this port - mpscrouting : the phandle for the MPSCROUTING node used by this port - mpscintr : the phandle for the MPSCINTR node used by this port - cell-index : the hardware index of this cell in the MPSC core - max_idle : value needed for MPSC CHR3 (Maximum Frame Length) register - interrupts : <a> where a is the interrupt number for the MPSC. - interrupt-parent : the phandle for the interrupt controller that services interrupts for this device. Example Discovery MPSCINTR node: mpsc@8000 { device_type = "serial"; compatible = "marvell,mv64360-mpsc"; reg = <0x8000 0x38>; virtual-reg = <0xf1008000>; sdma = <&SDMA0>; brg = <&BRG0>; cunit = <&CUNIT>; mpscrouting = <&MPSCROUTING>; mpscintr = <&MPSCINTR>; cell-index = <0>; max_idle = <40>; interrupts = <40>; interrupt-parent = <&PIC>; }; j) Marvell Discovery Watch Dog Timer nodes Represent the Discovery's watchdog timer hardware Required properties: - compatible : "marvell,mv64360-wdt" - reg : Offset and length of the register set for this device Example Discovery Watch Dog Timer node: wdt@b410 { compatible = "marvell,mv64360-wdt"; reg = <0xb410 0x8>; }; k) Marvell Discovery I2C nodes Represent the Discovery's I2C hardware Required properties: - device_type : "i2c" - compatible : "marvell,mv64360-i2c" - reg : Offset and length of the register set for this device - interrupts : <a> where a is the interrupt number for the I2C. - interrupt-parent : the phandle for the interrupt controller that services interrupts for this device. Example Discovery I2C node: compatible = "marvell,mv64360-i2c"; reg = <0xc000 0x20>; virtual-reg = <0xf100c000>; interrupts = <37>; interrupt-parent = <&PIC>; }; l) Marvell Discovery PIC (Programmable Interrupt Controller) nodes Represent the Discovery's PIC hardware Required properties: - #interrupt-cells : <1> - #address-cells : <0> - compatible : "marvell,mv64360-pic" - reg : Offset and length of the register set for this device - interrupt-controller Example Discovery PIC node: pic { #interrupt-cells = <1>; #address-cells = <0>; compatible = "marvell,mv64360-pic"; reg = <0x0 0x88>; interrupt-controller; }; m) Marvell Discovery MPP (Multipurpose Pins) multiplexing nodes Represent the Discovery's MPP hardware Required properties: - compatible : "marvell,mv64360-mpp" - reg : Offset and length of the register set for this device Example Discovery MPP node: mpp@f000 { compatible = "marvell,mv64360-mpp"; reg = <0xf000 0x10>; }; n) Marvell Discovery GPP (General Purpose Pins) nodes Represent the Discovery's GPP hardware Required properties: - compatible : "marvell,mv64360-gpp" - reg : Offset and length of the register set for this device Example Discovery GPP node: gpp@f000 { compatible = "marvell,mv64360-gpp"; reg = <0xf100 0x20>; }; o) Marvell Discovery PCI host bridge node Represents the Discovery's PCI host bridge device. The properties for this node conform to Rev 2.1 of the PCI Bus Binding to IEEE 1275-1994. A typical value for the compatible property is "marvell,mv64360-pci". Example Discovery PCI host bridge node pci@80000000 { #address-cells = <3>; #size-cells = <2>; #interrupt-cells = <1>; device_type = "pci"; compatible = "marvell,mv64360-pci"; reg = <0xcf8 0x8>; ranges = <0x01000000 0x0 0x0 0x88000000 0x0 0x01000000 0x02000000 0x0 0x80000000 0x80000000 0x0 0x08000000>; bus-range = <0 255>; clock-frequency = <66000000>; interrupt-parent = <&PIC>; interrupt-map-mask = <0xf800 0x0 0x0 0x7>; interrupt-map = < /* IDSEL 0x0a */ 0x5000 0 0 1 &PIC 80 0x5000 0 0 2 &PIC 81 0x5000 0 0 3 &PIC 91 0x5000 0 0 4 &PIC 93 /* IDSEL 0x0b */ 0x5800 0 0 1 &PIC 91 0x5800 0 0 2 &PIC 93 0x5800 0 0 3 &PIC 80 0x5800 0 0 4 &PIC 81 /* IDSEL 0x0c */ 0x6000 0 0 1 &PIC 91 0x6000 0 0 2 &PIC 93 0x6000 0 0 3 &PIC 80 0x6000 0 0 4 &PIC 81 /* IDSEL 0x0d */ 0x6800 0 0 1 &PIC 93 0x6800 0 0 2 &PIC 80 0x6800 0 0 3 &PIC 81 0x6800 0 0 4 &PIC 91 >; }; p) Marvell Discovery CPU Error nodes Represent the Discovery's CPU error handler device. Required properties: - compatible : "marvell,mv64360-cpu-error" - reg : Offset and length of the register set for this device - interrupts : the interrupt number for this device - interrupt-parent : the phandle for the interrupt controller that services interrupts for this device. Example Discovery CPU Error node: cpu-error@0070 { compatible = "marvell,mv64360-cpu-error"; reg = <0x70 0x10 0x128 0x28>; interrupts = <3>; interrupt-parent = <&PIC>; }; q) Marvell Discovery SRAM Controller nodes Represent the Discovery's SRAM controller device. Required properties: - compatible : "marvell,mv64360-sram-ctrl" - reg : Offset and length of the register set for this device - interrupts : the interrupt number for this device - interrupt-parent : the phandle for the interrupt controller that services interrupts for this device. Example Discovery SRAM Controller node: sram-ctrl@0380 { compatible = "marvell,mv64360-sram-ctrl"; reg = <0x380 0x80>; interrupts = <13>; interrupt-parent = <&PIC>; }; r) Marvell Discovery PCI Error Handler nodes Represent the Discovery's PCI error handler device. Required properties: - compatible : "marvell,mv64360-pci-error" - reg : Offset and length of the register set for this device - interrupts : the interrupt number for this device - interrupt-parent : the phandle for the interrupt controller that services interrupts for this device. Example Discovery PCI Error Handler node: pci-error@1d40 { compatible = "marvell,mv64360-pci-error"; reg = <0x1d40 0x40 0xc28 0x4>; interrupts = <12>; interrupt-parent = <&PIC>; }; s) Marvell Discovery Memory Controller nodes Represent the Discovery's memory controller device. Required properties: - compatible : "marvell,mv64360-mem-ctrl" - reg : Offset and length of the register set for this device - interrupts : the interrupt number for this device - interrupt-parent : the phandle for the interrupt controller that services interrupts for this device. Example Discovery Memory Controller node: mem-ctrl@1400 { compatible = "marvell,mv64360-mem-ctrl"; reg = <0x1400 0x60>; interrupts = <17>; interrupt-parent = <&PIC>; }; Loading
Documentation/powerpc/booting-without-of.txt +2 −1166 File changed.Preview size limit exceeded, changes collapsed. Show changes
Documentation/powerpc/dts-bindings/4xx/emac.txt 0 → 100644 +148 −0 Original line number Diff line number Diff line 4xx/Axon EMAC ethernet nodes The EMAC ethernet controller in IBM and AMCC 4xx chips, and also the Axon bridge. To operate this needs to interact with a ths special McMAL DMA controller, and sometimes an RGMII or ZMII interface. In addition to the nodes and properties described below, the node for the OPB bus on which the EMAC sits must have a correct clock-frequency property. i) The EMAC node itself Required properties: - device_type : "network" - compatible : compatible list, contains 2 entries, first is "ibm,emac-CHIP" where CHIP is the host ASIC (440gx, 405gp, Axon) and second is either "ibm,emac" or "ibm,emac4". For Axon, thus, we have: "ibm,emac-axon", "ibm,emac4" - interrupts : <interrupt mapping for EMAC IRQ and WOL IRQ> - interrupt-parent : optional, if needed for interrupt mapping - reg : <registers mapping> - local-mac-address : 6 bytes, MAC address - mal-device : phandle of the associated McMAL node - mal-tx-channel : 1 cell, index of the tx channel on McMAL associated with this EMAC - mal-rx-channel : 1 cell, index of the rx channel on McMAL associated with this EMAC - cell-index : 1 cell, hardware index of the EMAC cell on a given ASIC (typically 0x0 and 0x1 for EMAC0 and EMAC1 on each Axon chip) - max-frame-size : 1 cell, maximum frame size supported in bytes - rx-fifo-size : 1 cell, Rx fifo size in bytes for 10 and 100 Mb/sec operations. For Axon, 2048 - tx-fifo-size : 1 cell, Tx fifo size in bytes for 10 and 100 Mb/sec operations. For Axon, 2048. - fifo-entry-size : 1 cell, size of a fifo entry (used to calculate thresholds). For Axon, 0x00000010 - mal-burst-size : 1 cell, MAL burst size (used to calculate thresholds) in bytes. For Axon, 0x00000100 (I think ...) - phy-mode : string, mode of operations of the PHY interface. Supported values are: "mii", "rmii", "smii", "rgmii", "tbi", "gmii", rtbi", "sgmii". For Axon on CAB, it is "rgmii" - mdio-device : 1 cell, required iff using shared MDIO registers (440EP). phandle of the EMAC to use to drive the MDIO lines for the PHY used by this EMAC. - zmii-device : 1 cell, required iff connected to a ZMII. phandle of the ZMII device node - zmii-channel : 1 cell, required iff connected to a ZMII. Which ZMII channel or 0xffffffff if ZMII is only used for MDIO. - rgmii-device : 1 cell, required iff connected to an RGMII. phandle of the RGMII device node. For Axon: phandle of plb5/plb4/opb/rgmii - rgmii-channel : 1 cell, required iff connected to an RGMII. Which RGMII channel is used by this EMAC. Fox Axon: present, whatever value is appropriate for each EMAC, that is the content of the current (bogus) "phy-port" property. Optional properties: - phy-address : 1 cell, optional, MDIO address of the PHY. If absent, a search is performed. - phy-map : 1 cell, optional, bitmap of addresses to probe the PHY for, used if phy-address is absent. bit 0x00000001 is MDIO address 0. For Axon it can be absent, though my current driver doesn't handle phy-address yet so for now, keep 0x00ffffff in it. - rx-fifo-size-gige : 1 cell, Rx fifo size in bytes for 1000 Mb/sec operations (if absent the value is the same as rx-fifo-size). For Axon, either absent or 2048. - tx-fifo-size-gige : 1 cell, Tx fifo size in bytes for 1000 Mb/sec operations (if absent the value is the same as tx-fifo-size). For Axon, either absent or 2048. - tah-device : 1 cell, optional. If connected to a TAH engine for offload, phandle of the TAH device node. - tah-channel : 1 cell, optional. If appropriate, channel used on the TAH engine. Example: EMAC0: ethernet@40000800 { device_type = "network"; compatible = "ibm,emac-440gp", "ibm,emac"; interrupt-parent = <&UIC1>; interrupts = <1c 4 1d 4>; reg = <40000800 70>; local-mac-address = [00 04 AC E3 1B 1E]; mal-device = <&MAL0>; mal-tx-channel = <0 1>; mal-rx-channel = <0>; cell-index = <0>; max-frame-size = <5dc>; rx-fifo-size = <1000>; tx-fifo-size = <800>; phy-mode = "rmii"; phy-map = <00000001>; zmii-device = <&ZMII0>; zmii-channel = <0>; }; ii) McMAL node Required properties: - device_type : "dma-controller" - compatible : compatible list, containing 2 entries, first is "ibm,mcmal-CHIP" where CHIP is the host ASIC (like emac) and the second is either "ibm,mcmal" or "ibm,mcmal2". For Axon, "ibm,mcmal-axon","ibm,mcmal2" - interrupts : <interrupt mapping for the MAL interrupts sources: 5 sources: tx_eob, rx_eob, serr, txde, rxde>. For Axon: This is _different_ from the current firmware. We use the "delayed" interrupts for txeob and rxeob. Thus we end up with mapping those 5 MPIC interrupts, all level positive sensitive: 10, 11, 32, 33, 34 (in decimal) - dcr-reg : < DCR registers range > - dcr-parent : if needed for dcr-reg - num-tx-chans : 1 cell, number of Tx channels - num-rx-chans : 1 cell, number of Rx channels iii) ZMII node Required properties: - compatible : compatible list, containing 2 entries, first is "ibm,zmii-CHIP" where CHIP is the host ASIC (like EMAC) and the second is "ibm,zmii". For Axon, there is no ZMII node. - reg : <registers mapping> iv) RGMII node Required properties: - compatible : compatible list, containing 2 entries, first is "ibm,rgmii-CHIP" where CHIP is the host ASIC (like EMAC) and the second is "ibm,rgmii". For Axon, "ibm,rgmii-axon","ibm,rgmii" - reg : <registers mapping> - revision : as provided by the RGMII new version register if available. For Axon: 0x0000012a
Documentation/powerpc/dts-bindings/gpio/gpio.txt 0 → 100644 +50 −0 Original line number Diff line number Diff line Specifying GPIO information for devices ============================================ 1) gpios property ----------------- Nodes that makes use of GPIOs should define them using `gpios' property, format of which is: <&gpio-controller1-phandle gpio1-specifier &gpio-controller2-phandle gpio2-specifier 0 /* holes are permitted, means no GPIO 3 */ &gpio-controller4-phandle gpio4-specifier ...>; Note that gpio-specifier length is controller dependent. gpio-specifier may encode: bank, pin position inside the bank, whether pin is open-drain and whether pin is logically inverted. Example of the node using GPIOs: node { gpios = <&qe_pio_e 18 0>; }; In this example gpio-specifier is "18 0" and encodes GPIO pin number, and empty GPIO flags as accepted by the "qe_pio_e" gpio-controller. 2) gpio-controller nodes ------------------------ Every GPIO controller node must have #gpio-cells property defined, this information will be used to translate gpio-specifiers. Example of two SOC GPIO banks defined as gpio-controller nodes: qe_pio_a: gpio-controller@1400 { #gpio-cells = <2>; compatible = "fsl,qe-pario-bank-a", "fsl,qe-pario-bank"; reg = <0x1400 0x18>; gpio-controller; }; qe_pio_e: gpio-controller@1460 { #gpio-cells = <2>; compatible = "fsl,qe-pario-bank-e", "fsl,qe-pario-bank"; reg = <0x1460 0x18>; gpio-controller; };
Documentation/powerpc/dts-bindings/gpio/mdio.txt 0 → 100644 +19 −0 Original line number Diff line number Diff line MDIO on GPIOs Currently defined compatibles: - virtual,gpio-mdio MDC and MDIO lines connected to GPIO controllers are listed in the gpios property as described in section VIII.1 in the following order: MDC, MDIO. Example: mdio { compatible = "virtual,mdio-gpio"; #address-cells = <1>; #size-cells = <0>; gpios = <&qe_pio_a 11 &qe_pio_c 6>; };
Documentation/powerpc/dts-bindings/marvell.txt 0 → 100644 +521 −0 Original line number Diff line number Diff line Marvell Discovery mv64[345]6x System Controller chips =========================================================== The Marvell mv64[345]60 series of system controller chips contain many of the peripherals needed to implement a complete computer system. In this section, we define device tree nodes to describe the system controller chip itself and each of the peripherals which it contains. Compatible string values for each node are prefixed with the string "marvell,", for Marvell Technology Group Ltd. 1) The /system-controller node This node is used to represent the system-controller and must be present when the system uses a system controller chip. The top-level system-controller node contains information that is global to all devices within the system controller chip. The node name begins with "system-controller" followed by the unit address, which is the base address of the memory-mapped register set for the system controller chip. Required properties: - ranges : Describes the translation of system controller addresses for memory mapped registers. - clock-frequency: Contains the main clock frequency for the system controller chip. - reg : This property defines the address and size of the memory-mapped registers contained within the system controller chip. The address specified in the "reg" property should match the unit address of the system-controller node. - #address-cells : Address representation for system controller devices. This field represents the number of cells needed to represent the address of the memory-mapped registers of devices within the system controller chip. - #size-cells : Size representation for for the memory-mapped registers within the system controller chip. - #interrupt-cells : Defines the width of cells used to represent interrupts. Optional properties: - model : The specific model of the system controller chip. Such as, "mv64360", "mv64460", or "mv64560". - compatible : A string identifying the compatibility identifiers of the system controller chip. The system-controller node contains child nodes for each system controller device that the platform uses. Nodes should not be created for devices which exist on the system controller chip but are not used Example Marvell Discovery mv64360 system-controller node: system-controller@f1000000 { /* Marvell Discovery mv64360 */ #address-cells = <1>; #size-cells = <1>; model = "mv64360"; /* Default */ compatible = "marvell,mv64360"; clock-frequency = <133333333>; reg = <0xf1000000 0x10000>; virtual-reg = <0xf1000000>; ranges = <0x88000000 0x88000000 0x1000000 /* PCI 0 I/O Space */ 0x80000000 0x80000000 0x8000000 /* PCI 0 MEM Space */ 0xa0000000 0xa0000000 0x4000000 /* User FLASH */ 0x00000000 0xf1000000 0x0010000 /* Bridge's regs */ 0xf2000000 0xf2000000 0x0040000>;/* Integrated SRAM */ [ child node definitions... ] } 2) Child nodes of /system-controller a) Marvell Discovery MDIO bus The MDIO is a bus to which the PHY devices are connected. For each device that exists on this bus, a child node should be created. See the definition of the PHY node below for an example of how to define a PHY. Required properties: - #address-cells : Should be <1> - #size-cells : Should be <0> - device_type : Should be "mdio" - compatible : Should be "marvell,mv64360-mdio" Example: mdio { #address-cells = <1>; #size-cells = <0>; device_type = "mdio"; compatible = "marvell,mv64360-mdio"; ethernet-phy@0 { ...... }; }; b) Marvell Discovery ethernet controller The Discover ethernet controller is described with two levels of nodes. The first level describes an ethernet silicon block and the second level describes up to 3 ethernet nodes within that block. The reason for the multiple levels is that the registers for the node are interleaved within a single set of registers. The "ethernet-block" level describes the shared register set, and the "ethernet" nodes describe ethernet port-specific properties. Ethernet block node Required properties: - #address-cells : <1> - #size-cells : <0> - compatible : "marvell,mv64360-eth-block" - reg : Offset and length of the register set for this block Example Discovery Ethernet block node: ethernet-block@2000 { #address-cells = <1>; #size-cells = <0>; compatible = "marvell,mv64360-eth-block"; reg = <0x2000 0x2000>; ethernet@0 { ....... }; }; Ethernet port node Required properties: - device_type : Should be "network". - compatible : Should be "marvell,mv64360-eth". - reg : Should be <0>, <1>, or <2>, according to which registers within the silicon block the device uses. - interrupts : <a> where a is the interrupt number for the port. - interrupt-parent : the phandle for the interrupt controller that services interrupts for this device. - phy : the phandle for the PHY connected to this ethernet controller. - local-mac-address : 6 bytes, MAC address Example Discovery Ethernet port node: ethernet@0 { device_type = "network"; compatible = "marvell,mv64360-eth"; reg = <0>; interrupts = <32>; interrupt-parent = <&PIC>; phy = <&PHY0>; local-mac-address = [ 00 00 00 00 00 00 ]; }; c) Marvell Discovery PHY nodes Required properties: - device_type : Should be "ethernet-phy" - interrupts : <a> where a is the interrupt number for this phy. - interrupt-parent : the phandle for the interrupt controller that services interrupts for this device. - reg : The ID number for the phy, usually a small integer Example Discovery PHY node: ethernet-phy@1 { device_type = "ethernet-phy"; compatible = "broadcom,bcm5421"; interrupts = <76>; /* GPP 12 */ interrupt-parent = <&PIC>; reg = <1>; }; d) Marvell Discovery SDMA nodes Represent DMA hardware associated with the MPSC (multiprotocol serial controllers). Required properties: - compatible : "marvell,mv64360-sdma" - reg : Offset and length of the register set for this device - interrupts : <a> where a is the interrupt number for the DMA device. - interrupt-parent : the phandle for the interrupt controller that services interrupts for this device. Example Discovery SDMA node: sdma@4000 { compatible = "marvell,mv64360-sdma"; reg = <0x4000 0xc18>; virtual-reg = <0xf1004000>; interrupts = <36>; interrupt-parent = <&PIC>; }; e) Marvell Discovery BRG nodes Represent baud rate generator hardware associated with the MPSC (multiprotocol serial controllers). Required properties: - compatible : "marvell,mv64360-brg" - reg : Offset and length of the register set for this device - clock-src : A value from 0 to 15 which selects the clock source for the baud rate generator. This value corresponds to the CLKS value in the BRGx configuration register. See the mv64x60 User's Manual. - clock-frequence : The frequency (in Hz) of the baud rate generator's input clock. - current-speed : The current speed setting (presumably by firmware) of the baud rate generator. Example Discovery BRG node: brg@b200 { compatible = "marvell,mv64360-brg"; reg = <0xb200 0x8>; clock-src = <8>; clock-frequency = <133333333>; current-speed = <9600>; }; f) Marvell Discovery CUNIT nodes Represent the Serial Communications Unit device hardware. Required properties: - reg : Offset and length of the register set for this device Example Discovery CUNIT node: cunit@f200 { reg = <0xf200 0x200>; }; g) Marvell Discovery MPSCROUTING nodes Represent the Discovery's MPSC routing hardware Required properties: - reg : Offset and length of the register set for this device Example Discovery CUNIT node: mpscrouting@b500 { reg = <0xb400 0xc>; }; h) Marvell Discovery MPSCINTR nodes Represent the Discovery's MPSC DMA interrupt hardware registers (SDMA cause and mask registers). Required properties: - reg : Offset and length of the register set for this device Example Discovery MPSCINTR node: mpsintr@b800 { reg = <0xb800 0x100>; }; i) Marvell Discovery MPSC nodes Represent the Discovery's MPSC (Multiprotocol Serial Controller) serial port. Required properties: - device_type : "serial" - compatible : "marvell,mv64360-mpsc" - reg : Offset and length of the register set for this device - sdma : the phandle for the SDMA node used by this port - brg : the phandle for the BRG node used by this port - cunit : the phandle for the CUNIT node used by this port - mpscrouting : the phandle for the MPSCROUTING node used by this port - mpscintr : the phandle for the MPSCINTR node used by this port - cell-index : the hardware index of this cell in the MPSC core - max_idle : value needed for MPSC CHR3 (Maximum Frame Length) register - interrupts : <a> where a is the interrupt number for the MPSC. - interrupt-parent : the phandle for the interrupt controller that services interrupts for this device. Example Discovery MPSCINTR node: mpsc@8000 { device_type = "serial"; compatible = "marvell,mv64360-mpsc"; reg = <0x8000 0x38>; virtual-reg = <0xf1008000>; sdma = <&SDMA0>; brg = <&BRG0>; cunit = <&CUNIT>; mpscrouting = <&MPSCROUTING>; mpscintr = <&MPSCINTR>; cell-index = <0>; max_idle = <40>; interrupts = <40>; interrupt-parent = <&PIC>; }; j) Marvell Discovery Watch Dog Timer nodes Represent the Discovery's watchdog timer hardware Required properties: - compatible : "marvell,mv64360-wdt" - reg : Offset and length of the register set for this device Example Discovery Watch Dog Timer node: wdt@b410 { compatible = "marvell,mv64360-wdt"; reg = <0xb410 0x8>; }; k) Marvell Discovery I2C nodes Represent the Discovery's I2C hardware Required properties: - device_type : "i2c" - compatible : "marvell,mv64360-i2c" - reg : Offset and length of the register set for this device - interrupts : <a> where a is the interrupt number for the I2C. - interrupt-parent : the phandle for the interrupt controller that services interrupts for this device. Example Discovery I2C node: compatible = "marvell,mv64360-i2c"; reg = <0xc000 0x20>; virtual-reg = <0xf100c000>; interrupts = <37>; interrupt-parent = <&PIC>; }; l) Marvell Discovery PIC (Programmable Interrupt Controller) nodes Represent the Discovery's PIC hardware Required properties: - #interrupt-cells : <1> - #address-cells : <0> - compatible : "marvell,mv64360-pic" - reg : Offset and length of the register set for this device - interrupt-controller Example Discovery PIC node: pic { #interrupt-cells = <1>; #address-cells = <0>; compatible = "marvell,mv64360-pic"; reg = <0x0 0x88>; interrupt-controller; }; m) Marvell Discovery MPP (Multipurpose Pins) multiplexing nodes Represent the Discovery's MPP hardware Required properties: - compatible : "marvell,mv64360-mpp" - reg : Offset and length of the register set for this device Example Discovery MPP node: mpp@f000 { compatible = "marvell,mv64360-mpp"; reg = <0xf000 0x10>; }; n) Marvell Discovery GPP (General Purpose Pins) nodes Represent the Discovery's GPP hardware Required properties: - compatible : "marvell,mv64360-gpp" - reg : Offset and length of the register set for this device Example Discovery GPP node: gpp@f000 { compatible = "marvell,mv64360-gpp"; reg = <0xf100 0x20>; }; o) Marvell Discovery PCI host bridge node Represents the Discovery's PCI host bridge device. The properties for this node conform to Rev 2.1 of the PCI Bus Binding to IEEE 1275-1994. A typical value for the compatible property is "marvell,mv64360-pci". Example Discovery PCI host bridge node pci@80000000 { #address-cells = <3>; #size-cells = <2>; #interrupt-cells = <1>; device_type = "pci"; compatible = "marvell,mv64360-pci"; reg = <0xcf8 0x8>; ranges = <0x01000000 0x0 0x0 0x88000000 0x0 0x01000000 0x02000000 0x0 0x80000000 0x80000000 0x0 0x08000000>; bus-range = <0 255>; clock-frequency = <66000000>; interrupt-parent = <&PIC>; interrupt-map-mask = <0xf800 0x0 0x0 0x7>; interrupt-map = < /* IDSEL 0x0a */ 0x5000 0 0 1 &PIC 80 0x5000 0 0 2 &PIC 81 0x5000 0 0 3 &PIC 91 0x5000 0 0 4 &PIC 93 /* IDSEL 0x0b */ 0x5800 0 0 1 &PIC 91 0x5800 0 0 2 &PIC 93 0x5800 0 0 3 &PIC 80 0x5800 0 0 4 &PIC 81 /* IDSEL 0x0c */ 0x6000 0 0 1 &PIC 91 0x6000 0 0 2 &PIC 93 0x6000 0 0 3 &PIC 80 0x6000 0 0 4 &PIC 81 /* IDSEL 0x0d */ 0x6800 0 0 1 &PIC 93 0x6800 0 0 2 &PIC 80 0x6800 0 0 3 &PIC 81 0x6800 0 0 4 &PIC 91 >; }; p) Marvell Discovery CPU Error nodes Represent the Discovery's CPU error handler device. Required properties: - compatible : "marvell,mv64360-cpu-error" - reg : Offset and length of the register set for this device - interrupts : the interrupt number for this device - interrupt-parent : the phandle for the interrupt controller that services interrupts for this device. Example Discovery CPU Error node: cpu-error@0070 { compatible = "marvell,mv64360-cpu-error"; reg = <0x70 0x10 0x128 0x28>; interrupts = <3>; interrupt-parent = <&PIC>; }; q) Marvell Discovery SRAM Controller nodes Represent the Discovery's SRAM controller device. Required properties: - compatible : "marvell,mv64360-sram-ctrl" - reg : Offset and length of the register set for this device - interrupts : the interrupt number for this device - interrupt-parent : the phandle for the interrupt controller that services interrupts for this device. Example Discovery SRAM Controller node: sram-ctrl@0380 { compatible = "marvell,mv64360-sram-ctrl"; reg = <0x380 0x80>; interrupts = <13>; interrupt-parent = <&PIC>; }; r) Marvell Discovery PCI Error Handler nodes Represent the Discovery's PCI error handler device. Required properties: - compatible : "marvell,mv64360-pci-error" - reg : Offset and length of the register set for this device - interrupts : the interrupt number for this device - interrupt-parent : the phandle for the interrupt controller that services interrupts for this device. Example Discovery PCI Error Handler node: pci-error@1d40 { compatible = "marvell,mv64360-pci-error"; reg = <0x1d40 0x40 0xc28 0x4>; interrupts = <12>; interrupt-parent = <&PIC>; }; s) Marvell Discovery Memory Controller nodes Represent the Discovery's memory controller device. Required properties: - compatible : "marvell,mv64360-mem-ctrl" - reg : Offset and length of the register set for this device - interrupts : the interrupt number for this device - interrupt-parent : the phandle for the interrupt controller that services interrupts for this device. Example Discovery Memory Controller node: mem-ctrl@1400 { compatible = "marvell,mv64360-mem-ctrl"; reg = <0x1400 0x60>; interrupts = <17>; interrupt-parent = <&PIC>; };
