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Allwinner A31 SPI controller

Allwinner A31/H3 SPI controller

Required properties:

- compatible: Should be "allwinner,sun6i-a31-spi".

- compatible: Should be "allwinner,sun6i-a31-spi" or "allwinner,sun8i-h3-spi".

- reg: Should contain register location and length.

- interrupts: Should contain interrupt.

- clocks: phandle to the clocks feeding the SPI controller. Two are

- resets: phandle to the reset controller asserting this device in

          reset

Optional properties:

- dmas: DMA specifiers for rx and tx dma. See the DMA client binding,

	Documentation/devicetree/bindings/dma/dma.txt

- dma-names: DMA request names should include "rx" and "tx" if present.

Example:

spi1: spi@01c69000 {

	clock-names = "ahb", "mod";

	resets = <&ahb1_rst 21>;

};

spi0: spi@01c68000 {

	compatible = "allwinner,sun8i-h3-spi";

	reg = <0x01c68000 0x1000>;

	interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;

	clocks = <&ccu CLK_BUS_SPI0>, <&ccu CLK_SPI0>;

	clock-names = "ahb", "mod";

	dmas = <&dma 23>, <&dma 23>;

	dma-names = "rx", "tx";

	pinctrl-names = "default";

	pinctrl-0 = <&spi0_pins>;

	resets = <&ccu RST_BUS_SPI0>;

	status = "disabled";

	#address-cells = <1>;

	#size-cells = <0>;

};

#define SUN4I_CTL_TP				BIT(18)

#define SUN4I_INT_CTL_REG		0x0c

#define SUN4I_INT_CTL_RF_F34			BIT(4)

#define SUN4I_INT_CTL_TF_E34			BIT(12)

#define SUN4I_INT_CTL_TC			BIT(16)

#define SUN4I_INT_STA_REG		0x10

#define SUN4I_CLK_CTL_CDR1(div)			(((div) & SUN4I_CLK_CTL_CDR1_MASK) << 8)

#define SUN4I_CLK_CTL_DRS			BIT(12)

#define SUN4I_MAX_XFER_SIZE			0xffffff

#define SUN4I_BURST_CNT_REG		0x20

#define SUN4I_BURST_CNT(cnt)			((cnt) & 0xffffff)

#define SUN4I_BURST_CNT(cnt)			((cnt) & SUN4I_MAX_XFER_SIZE)

#define SUN4I_XMIT_CNT_REG		0x24

#define SUN4I_XMIT_CNT(cnt)			((cnt) & 0xffffff)

#define SUN4I_XMIT_CNT(cnt)			((cnt) & SUN4I_MAX_XFER_SIZE)

#define SUN4I_FIFO_STA_REG		0x28

#define SUN4I_FIFO_STA_RF_CNT_MASK		0x7f

	writel(value, sspi->base_addr + reg);

}

static inline u32 sun4i_spi_get_tx_fifo_count(struct sun4i_spi *sspi)

{

	u32 reg = sun4i_spi_read(sspi, SUN4I_FIFO_STA_REG);

	reg >>= SUN4I_FIFO_STA_TF_CNT_BITS;

	return reg & SUN4I_FIFO_STA_TF_CNT_MASK;

}

static inline void sun4i_spi_enable_interrupt(struct sun4i_spi *sspi, u32 mask)

{

	u32 reg = sun4i_spi_read(sspi, SUN4I_INT_CTL_REG);

	reg |= mask;

	sun4i_spi_write(sspi, SUN4I_INT_CTL_REG, reg);

}

static inline void sun4i_spi_disable_interrupt(struct sun4i_spi *sspi, u32 mask)

{

	u32 reg = sun4i_spi_read(sspi, SUN4I_INT_CTL_REG);

	reg &= ~mask;

	sun4i_spi_write(sspi, SUN4I_INT_CTL_REG, reg);

}

static inline void sun4i_spi_drain_fifo(struct sun4i_spi *sspi, int len)

{

	u32 reg, cnt;

static inline void sun4i_spi_fill_fifo(struct sun4i_spi *sspi, int len)

{

	u32 cnt;

	u8 byte;

	if (len > sspi->len)

		len = sspi->len;

	/* See how much data we can fit */

	cnt = SUN4I_FIFO_DEPTH - sun4i_spi_get_tx_fifo_count(sspi);

	len = min3(len, (int)cnt, sspi->len);

	while (len--) {

		byte = sspi->tx_buf ? *sspi->tx_buf++ : 0;

	u32 reg;

	/* We don't support transfer larger than the FIFO */

	if (tfr->len > SUN4I_FIFO_DEPTH)

	if (tfr->len > SUN4I_MAX_XFER_SIZE)

		return -EMSGSIZE;

	if (tfr->tx_buf && tfr->len >= SUN4I_FIFO_DEPTH)

	if (tfr->tx_buf && tfr->len >= SUN4I_MAX_XFER_SIZE)

		return -EMSGSIZE;

	reinit_completion(&sspi->done);

	sun4i_spi_fill_fifo(sspi, SUN4I_FIFO_DEPTH - 1);

	/* Enable the interrupts */

	sun4i_spi_write(sspi, SUN4I_INT_CTL_REG, SUN4I_INT_CTL_TC);

	sun4i_spi_enable_interrupt(sspi, SUN4I_INT_CTL_TC |

					 SUN4I_INT_CTL_RF_F34);

	/* Only enable Tx FIFO interrupt if we really need it */

	if (tx_len > SUN4I_FIFO_DEPTH)

		sun4i_spi_enable_interrupt(sspi, SUN4I_INT_CTL_TF_E34);

	/* Start the transfer */

	reg = sun4i_spi_read(sspi, SUN4I_CTL_REG);

		goto out;

	}

	sun4i_spi_drain_fifo(sspi, SUN4I_FIFO_DEPTH);

out:

	sun4i_spi_write(sspi, SUN4I_INT_CTL_REG, 0);

	/* Transfer complete */

	if (status & SUN4I_INT_CTL_TC) {

		sun4i_spi_write(sspi, SUN4I_INT_STA_REG, SUN4I_INT_CTL_TC);

		sun4i_spi_drain_fifo(sspi, SUN4I_FIFO_DEPTH);

		complete(&sspi->done);

		return IRQ_HANDLED;

	}

	/* Receive FIFO 3/4 full */

	if (status & SUN4I_INT_CTL_RF_F34) {

		sun4i_spi_drain_fifo(sspi, SUN4I_FIFO_DEPTH);

		/* Only clear the interrupt _after_ draining the FIFO */

		sun4i_spi_write(sspi, SUN4I_INT_STA_REG, SUN4I_INT_CTL_RF_F34);

		return IRQ_HANDLED;

	}

	/* Transmit FIFO 3/4 empty */

	if (status & SUN4I_INT_CTL_TF_E34) {

		sun4i_spi_fill_fifo(sspi, SUN4I_FIFO_DEPTH);

		if (!sspi->len)

			/* nothing left to transmit */

			sun4i_spi_disable_interrupt(sspi, SUN4I_INT_CTL_TF_E34);

		/* Only clear the interrupt _after_ re-seeding the FIFO */

		sun4i_spi_write(sspi, SUN4I_INT_STA_REG, SUN4I_INT_CTL_TF_E34);

		return IRQ_HANDLED;

	}

	return IRQ_NONE;

}

#include <linux/interrupt.h>

#include <linux/io.h>

#include <linux/module.h>

#include <linux/of_device.h>

#include <linux/platform_device.h>

#include <linux/pm_runtime.h>

#include <linux/reset.h>

#include <linux/spi/spi.h>

#define SUN6I_FIFO_DEPTH		128

#define SUN8I_FIFO_DEPTH		64

#define SUN6I_GBL_CTL_REG		0x04

#define SUN6I_GBL_CTL_BUS_ENABLE		BIT(0)

	const u8		*tx_buf;

	u8			*rx_buf;

	int			len;

	unsigned long		fifo_depth;

};

static inline u32 sun6i_spi_read(struct sun6i_spi *sspi, u32 reg)

static size_t sun6i_spi_max_transfer_size(struct spi_device *spi)

{

	return SUN6I_FIFO_DEPTH - 1;

	struct sun6i_spi *sspi = spi_master_get_devdata(spi->master);

	return sspi->fifo_depth - 1;

}

static int sun6i_spi_transfer_one(struct spi_master *master,

	u32 reg;

	/* We don't support transfer larger than the FIFO */

	if (tfr->len > SUN6I_FIFO_DEPTH)

	if (tfr->len > sspi->fifo_depth)

		return -EINVAL;

	reinit_completion(&sspi->done);

			SUN6I_BURST_CTL_CNT_STC(tx_len));

	/* Fill the TX FIFO */

	sun6i_spi_fill_fifo(sspi, SUN6I_FIFO_DEPTH);

	sun6i_spi_fill_fifo(sspi, sspi->fifo_depth);

	/* Enable the interrupts */

	sun6i_spi_write(sspi, SUN6I_INT_CTL_REG, SUN6I_INT_CTL_TC);

		goto out;

	}

	sun6i_spi_drain_fifo(sspi, SUN6I_FIFO_DEPTH);

	sun6i_spi_drain_fifo(sspi, sspi->fifo_depth);

out:

	sun6i_spi_write(sspi, SUN6I_INT_CTL_REG, 0);

	}

	sspi->master = master;

	sspi->fifo_depth = (unsigned long)of_device_get_match_data(&pdev->dev);

	master->max_speed_hz = 100 * 1000 * 1000;

	master->min_speed_hz = 3 * 1000;

	master->set_cs = sun6i_spi_set_cs;

}

static const struct of_device_id sun6i_spi_match[] = {

	{ .compatible = "allwinner,sun6i-a31-spi", },

	{ .compatible = "allwinner,sun6i-a31-spi", .data = (void *)SUN6I_FIFO_DEPTH },

	{ .compatible = "allwinner,sun8i-h3-spi",  .data = (void *)SUN8I_FIFO_DEPTH },

	{}

};

MODULE_DEVICE_TABLE(of, sun6i_spi_match);

	tx->callback = ti_qspi_dma_callback;

	tx->callback_param = qspi;

	cookie = tx->tx_submit(tx);

	reinit_completion(&qspi->transfer_complete);

	ret = dma_submit_error(cookie);

	if (ret) {

static int pch_spi_get_resources(struct pch_spi_board_data *board_dat,

				 struct pch_spi_data *data)

{

	int retval = 0;

	dev_dbg(&board_dat->pdev->dev, "%s ENTRY\n", __func__);

	/* reset PCH SPI h/w */

	pch_spi_reset(data->master);

	dev_dbg(&board_dat->pdev->dev,

	dev_dbg(&board_dat->pdev->dev, "%s data->irq_reg_sts=true\n", __func__);

	if (retval != 0) {

		dev_err(&board_dat->pdev->dev,

			"%s FAIL:invoking pch_spi_free_resources\n", __func__);

		pch_spi_free_resources(board_dat, data);

	}

	dev_dbg(&board_dat->pdev->dev, "%s Return=%d\n", __func__, retval);

	return retval;

	return 0;

}

static void pch_free_dma_buf(struct pch_spi_board_data *board_dat,