Commit fad25222 authored Jan 04, 2016 by John Crispin Committed by Ralf Baechle Jan 20, 2016

MIPS: ralink: fix USB frequency scaling



Commit 418d29c8 ("MIPS: ralink: Unify SoC id handling") was not fully
correct. The logic for the SoC check got inverted. We need to check if it
is not a MT76x8.

Signed-off-by: John Crispin <blogic@openwrt.org>
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/11992/


Signed-off-by: Ralf Baechle <ralf@linux-mips.org>

parent e906a5f6

arch/mips/ralink/mt7620.c

+1 −1

Original line number	Diff line number	Diff line
		@@ -459,7 +459,7 @@ void __init ralink_clk_init(void)
		ralink_clk_add("10000c00.uartlite", periph_rate);
		ralink_clk_add("10180000.wmac", xtal_rate);

		if (IS_ENABLED(CONFIG_USB) && is_mt76x8()) {
		if (IS_ENABLED(CONFIG_USB) && !is_mt76x8()) {
		/*
		* When the CPU goes into sleep mode, the BUS clock will be
		* too low for USB to function properly. Adjust the busses