drm/nouveau/kms/gv100: initial support (facaed62) · Commits · e / devices / android_kernel_teracube_emerald

drivers/gpu/drm/nouveau/dispnv50/Kbuild

+8 −0

Original line number	Diff line number	Diff line
		@@ -6,6 +6,7 @@ nouveau-y += dispnv50/core507d.o
		nouveau-y += dispnv50/core827d.o
		nouveau-y += dispnv50/core907d.o
		nouveau-y += dispnv50/core917d.o
		nouveau-y += dispnv50/corec37d.o

		nouveau-y += dispnv50/dac507d.o
		nouveau-y += dispnv50/dac907d.o
		@@ -14,14 +15,20 @@ nouveau-y += dispnv50/pior507d.o

		nouveau-y += dispnv50/sor507d.o
		nouveau-y += dispnv50/sor907d.o
		nouveau-y += dispnv50/sorc37d.o

		nouveau-y += dispnv50/head.o
		nouveau-y += dispnv50/head507d.o
		nouveau-y += dispnv50/head827d.o
		nouveau-y += dispnv50/head907d.o
		nouveau-y += dispnv50/head917d.o
		nouveau-y += dispnv50/headc37d.o

		nouveau-y += dispnv50/wimm.o
		nouveau-y += dispnv50/wimmc37b.o

		nouveau-y += dispnv50/wndw.o
		nouveau-y += dispnv50/wndwc37e.o

		nouveau-y += dispnv50/base.o
		nouveau-y += dispnv50/base507c.o
		@@ -32,6 +39,7 @@ nouveau-y += dispnv50/base917c.o
		nouveau-y += dispnv50/curs.o
		nouveau-y += dispnv50/curs507a.o
		nouveau-y += dispnv50/curs907a.o
		nouveau-y += dispnv50/cursc37a.o

		nouveau-y += dispnv50/oimm.o
		nouveau-y += dispnv50/oimm507b.o

drivers/gpu/drm/nouveau/dispnv50/atom.h

+7 −1

Original line number	Diff line number	Diff line
		@@ -54,6 +54,9 @@ struct nv50_head_atom {
		u64 offset:40;
		u8 buffer:1;
		u8 mode:4;
		u8 size:2;
		u8 range:2;
		u8 output_mode:2;
		} olut;

		struct {
		@@ -77,7 +80,7 @@ struct nv50_head_atom {
		u32 handle;
		u64 offset:40;
		u8 layout:2;
		u8 format:1;
		u8 format:8;
		} curs;

		struct {
		@@ -166,6 +169,9 @@ struct nv50_wndw_atom {
		u8 buffer:1;
		u8 enable:2;
		u8 mode:4;
		u8 size:2;
		u8 range:2;
		u8 output_mode:2;
		} i;
		} xlut;

drivers/gpu/drm/nouveau/dispnv50/core.c

+1 −0

Original line number	Diff line number	Diff line
		@@ -42,6 +42,7 @@ nv50_core_new(struct nouveau_drm drm, struct nv50_core *pcore)
		int version;
		int (new)(struct nouveau_drm , s32, struct nv50_core **);
		} cores[] = {
		{ GV100_DISP_CORE_CHANNEL_DMA, 0, corec37d_new },
		{ GP102_DISP_CORE_CHANNEL_DMA, 0, core917d_new },
		{ GP100_DISP_CORE_CHANNEL_DMA, 0, core917d_new },
		{ GM200_DISP_CORE_CHANNEL_DMA, 0, core917d_new },

drivers/gpu/drm/nouveau/dispnv50/core.h

+3 −0

Original line number	Diff line number	Diff line
		@@ -44,4 +44,7 @@ extern const struct nv50_outp_func dac907d;
		extern const struct nv50_outp_func sor907d;

		int core917d_new(struct nouveau_drm , s32, struct nv50_core *);

		int corec37d_new(struct nouveau_drm , s32, struct nv50_core *);
		extern const struct nv50_outp_func sorc37d;
		#endif

drivers/gpu/drm/nouveau/dispnv50/corec37d.c

0 → 100644

+110 −0

Original line number	Diff line number	Diff line
		/*
		* Copyright 2018 Red Hat Inc.
		*
		* Permission is hereby granted, free of charge, to any person obtaining a
		* copy of this software and associated documentation files (the "Software"),
		* to deal in the Software without restriction, including without limitation
		* the rights to use, copy, modify, merge, publish, distribute, sublicense,
		* and/or sell copies of the Software, and to permit persons to whom the
		* Software is furnished to do so, subject to the following conditions:
		*
		* The above copyright notice and this permission notice shall be included in
		* all copies or substantial portions of the Software.
		*
		* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
		* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
		* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
		* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
		* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
		* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
		* OTHER DEALINGS IN THE SOFTWARE.
		*/
		#include "core.h"
		#include "head.h"

		#include <nouveau_bo.h>

		static void
		corec37d_update(struct nv50_core core, u32 interlock, bool ntfy)
		{
		u32 *push;
		if ((push = evo_wait(&core->chan, 9))) {
		if (ntfy) {
		evo_mthd(push, 0x020c, 1);
		evo_data(push, 0x00001000 \| NV50_DISP_CORE_NTFY);
		}

		evo_mthd(push, 0x0218, 2);
		evo_data(push, interlock[NV50_DISP_INTERLOCK_CURS]);
		evo_data(push, interlock[NV50_DISP_INTERLOCK_WNDW]);
		evo_mthd(push, 0x0200, 1);
		evo_data(push, 0x00000001);

		if (ntfy) {
		evo_mthd(push, 0x020c, 1);
		evo_data(push, 0x00000000);
		}
		evo_kick(push, &core->chan);
		}
		}

		int
		corec37d_ntfy_wait_done(struct nouveau_bo *bo, u32 offset,
		struct nvif_device *device)
		{
		u32 data;
		s64 time = nvif_msec(device, 2000ULL,
		data = nouveau_bo_rd32(bo, offset / 4 + 0);
		if ((data & 0xc0000000) == 0x80000000)
		break;
		usleep_range(1, 2);
		);
		return time < 0 ? time : 0;
		}

		void
		corec37d_ntfy_init(struct nouveau_bo *bo, u32 offset)
		{
		nouveau_bo_wr32(bo, offset / 4 + 0, 0x00000000);
		nouveau_bo_wr32(bo, offset / 4 + 1, 0x00000000);
		nouveau_bo_wr32(bo, offset / 4 + 2, 0x00000000);
		nouveau_bo_wr32(bo, offset / 4 + 3, 0x00000000);
		}

		void
		corec37d_init(struct nv50_core *core)
		{
		const u32 windows = 8; /XXX/
		u32 *push, i;
		if ((push = evo_wait(&core->chan, 2 + 6 * windows + 2))) {
		evo_mthd(push, 0x0208, 1);
		evo_data(push, core->chan.sync.handle);
		for (i = 0; i < windows; i++) {
		evo_mthd(push, 0x1000 + (i * 0x080), 3);
		evo_data(push, i >> 1);
		evo_data(push, 0x00000017);
		evo_data(push, 0x00000000);
		evo_mthd(push, 0x1010 + (i * 0x080), 1);
		evo_data(push, 0x00127fff);
		}
		evo_mthd(push, 0x0200, 1);
		evo_data(push, 0x00000001);
		evo_kick(push, &core->chan);
		}
		}

		static const struct nv50_core_func
		corec37d = {
		.init = corec37d_init,
		.ntfy_init = corec37d_ntfy_init,
		.ntfy_wait_done = corec37d_ntfy_wait_done,
		.update = corec37d_update,
		.head = &headc37d,
		.sor = &sorc37d,
		};

		int
		corec37d_new(struct nouveau_drm drm, s32 oclass, struct nv50_core *pcore)
		{
		return core507d_new_(&corec37d, drm, oclass, pcore);
		}