Merge remote-tracking branches 'asoc/topic/max98927', 'asoc/topic/mc13783',... (fab9298c) · Commits · e / devices / android_kernel_teracube_emerald

Documentation/devicetree/bindings/sound/mt2701-afe-pcm.txt

+128 −138

Original line number	Original line	Diff line number	Diff line
	@@ -2,153 +2,143 @@ Mediatek AFE PCM controller for mt2701

	Required properties:		Required properties:
	- compatible = "mediatek,mt2701-audio";		- compatible = "mediatek,mt2701-audio";
	- reg: register location and size
	- interrupts: should contain AFE and ASYS interrupts		- interrupts: should contain AFE and ASYS interrupts
	- interrupt-names: should be "afe" and "asys"		- interrupt-names: should be "afe" and "asys"
	- power-domains: should define the power domain		- power-domains: should define the power domain
			- clocks: Must contain an entry for each entry in clock-names
			See ../clocks/clock-bindings.txt for details
	- clock-names: should have these clock names:		- clock-names: should have these clock names:
	"infra_sys_audio_clk",		"infra_sys_audio_clk",
	"top_audio_mux1_sel",		"top_audio_mux1_sel",
	"top_audio_mux2_sel",		"top_audio_mux2_sel",
	"top_audio_mux1_div",		"top_audio_a1sys_hp",
	"top_audio_mux2_div",		"top_audio_a2sys_hp",
	"top_audio_48k_timing",		"i2s0_src_sel",
	"top_audio_44k_timing",		"i2s1_src_sel",
	"top_audpll_mux_sel",		"i2s2_src_sel",
	"top_apll_sel",		"i2s3_src_sel",
	"top_aud1_pll_98M",		"i2s0_src_div",
	"top_aud2_pll_90M",		"i2s1_src_div",
	"top_hadds2_pll_98M",		"i2s2_src_div",
	"top_hadds2_pll_294M",		"i2s3_src_div",
	"top_audpll",		"i2s0_mclk_en",
	"top_audpll_d4",		"i2s1_mclk_en",
	"top_audpll_d8",		"i2s2_mclk_en",
	"top_audpll_d16",		"i2s3_mclk_en",
	"top_audpll_d24",		"i2so0_hop_ck",
	"top_audintbus_sel",		"i2so1_hop_ck",
	"clk_26m",		"i2so2_hop_ck",
	"top_syspll1_d4",		"i2so3_hop_ck",
	"top_aud_k1_src_sel",		"i2si0_hop_ck",
	"top_aud_k2_src_sel",		"i2si1_hop_ck",
	"top_aud_k3_src_sel",		"i2si2_hop_ck",
	"top_aud_k4_src_sel",		"i2si3_hop_ck",
	"top_aud_k5_src_sel",		"asrc0_out_ck",
	"top_aud_k6_src_sel",		"asrc1_out_ck",
	"top_aud_k1_src_div",		"asrc2_out_ck",
	"top_aud_k2_src_div",		"asrc3_out_ck",
	"top_aud_k3_src_div",		"audio_afe_pd",
	"top_aud_k4_src_div",		"audio_afe_conn_pd",
	"top_aud_k5_src_div",		"audio_a1sys_pd",
	"top_aud_k6_src_div",		"audio_a2sys_pd",
	"top_aud_i2s1_mclk",		"audio_mrgif_pd";
	"top_aud_i2s2_mclk",		- assigned-clocks: list of input clocks and dividers for the audio system.
	"top_aud_i2s3_mclk",		See ../clocks/clock-bindings.txt for details.
	"top_aud_i2s4_mclk",		- assigned-clocks-parents: parent of input clocks of assigned clocks.
	"top_aud_i2s5_mclk",		- assigned-clock-rates: list of clock frequencies of assigned clocks.
	"top_aud_i2s6_mclk",
	"top_asm_m_sel",		Must be a subnode of MediaTek audsys device tree node.
	"top_asm_h_sel",		See ../arm/mediatek/mediatek,audsys.txt for details about the parent node.
	"top_univpll2_d4",
	"top_univpll2_d2",
	"top_syspll_d5";

	Example:		Example:

	afe: mt2701-afe-pcm@11220000 {		audsys: audio-subsystem@11220000 {
			compatible = "mediatek,mt2701-audsys", "syscon", "simple-mfd";
			...

			afe: audio-controller {
	compatible = "mediatek,mt2701-audio";		compatible = "mediatek,mt2701-audio";
	reg = <0 0x11220000 0 0x2000>,
	<0 0x112A0000 0 0x20000>;
	interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_LOW>,		interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_LOW>,
	<GIC_SPI 132 IRQ_TYPE_LEVEL_LOW>;		<GIC_SPI 132 IRQ_TYPE_LEVEL_LOW>;
	interrupt-names = "afe", "asys";		interrupt-names = "afe", "asys";
	power-domains = <&scpsys MT2701_POWER_DOMAIN_IFR_MSC>;		power-domains = <&scpsys MT2701_POWER_DOMAIN_IFR_MSC>;

	clocks = <&infracfg CLK_INFRA_AUDIO>,		clocks = <&infracfg CLK_INFRA_AUDIO>,
	<&topckgen CLK_TOP_AUD_MUX1_SEL>,		<&topckgen CLK_TOP_AUD_MUX1_SEL>,
	<&topckgen CLK_TOP_AUD_MUX2_SEL>,		<&topckgen CLK_TOP_AUD_MUX2_SEL>,
	<&topckgen CLK_TOP_AUD_MUX1_DIV>,
	<&topckgen CLK_TOP_AUD_MUX2_DIV>,
	<&topckgen CLK_TOP_AUD_48K_TIMING>,		<&topckgen CLK_TOP_AUD_48K_TIMING>,
	<&topckgen CLK_TOP_AUD_44K_TIMING>,		<&topckgen CLK_TOP_AUD_44K_TIMING>,
	<&topckgen CLK_TOP_AUDPLL_MUX_SEL>,
	<&topckgen CLK_TOP_APLL_SEL>,
	<&topckgen CLK_TOP_AUD1PLL_98M>,
	<&topckgen CLK_TOP_AUD2PLL_90M>,
	<&topckgen CLK_TOP_HADDS2PLL_98M>,
	<&topckgen CLK_TOP_HADDS2PLL_294M>,
	<&topckgen CLK_TOP_AUDPLL>,
	<&topckgen CLK_TOP_AUDPLL_D4>,
	<&topckgen CLK_TOP_AUDPLL_D8>,
	<&topckgen CLK_TOP_AUDPLL_D16>,
	<&topckgen CLK_TOP_AUDPLL_D24>,
	<&topckgen CLK_TOP_AUDINTBUS_SEL>,
	<&clk26m>,
	<&topckgen CLK_TOP_SYSPLL1_D4>,
	<&topckgen CLK_TOP_AUD_K1_SRC_SEL>,		<&topckgen CLK_TOP_AUD_K1_SRC_SEL>,
	<&topckgen CLK_TOP_AUD_K2_SRC_SEL>,		<&topckgen CLK_TOP_AUD_K2_SRC_SEL>,
	<&topckgen CLK_TOP_AUD_K3_SRC_SEL>,		<&topckgen CLK_TOP_AUD_K3_SRC_SEL>,
	<&topckgen CLK_TOP_AUD_K4_SRC_SEL>,		<&topckgen CLK_TOP_AUD_K4_SRC_SEL>,
	<&topckgen CLK_TOP_AUD_K5_SRC_SEL>,
	<&topckgen CLK_TOP_AUD_K6_SRC_SEL>,
	<&topckgen CLK_TOP_AUD_K1_SRC_DIV>,		<&topckgen CLK_TOP_AUD_K1_SRC_DIV>,
	<&topckgen CLK_TOP_AUD_K2_SRC_DIV>,		<&topckgen CLK_TOP_AUD_K2_SRC_DIV>,
	<&topckgen CLK_TOP_AUD_K3_SRC_DIV>,		<&topckgen CLK_TOP_AUD_K3_SRC_DIV>,
	<&topckgen CLK_TOP_AUD_K4_SRC_DIV>,		<&topckgen CLK_TOP_AUD_K4_SRC_DIV>,
	<&topckgen CLK_TOP_AUD_K5_SRC_DIV>,
	<&topckgen CLK_TOP_AUD_K6_SRC_DIV>,
	<&topckgen CLK_TOP_AUD_I2S1_MCLK>,		<&topckgen CLK_TOP_AUD_I2S1_MCLK>,
	<&topckgen CLK_TOP_AUD_I2S2_MCLK>,		<&topckgen CLK_TOP_AUD_I2S2_MCLK>,
	<&topckgen CLK_TOP_AUD_I2S3_MCLK>,		<&topckgen CLK_TOP_AUD_I2S3_MCLK>,
	<&topckgen CLK_TOP_AUD_I2S4_MCLK>,		<&topckgen CLK_TOP_AUD_I2S4_MCLK>,
	<&topckgen CLK_TOP_AUD_I2S5_MCLK>,		<&audsys CLK_AUD_I2SO1>,
	<&topckgen CLK_TOP_AUD_I2S6_MCLK>,		<&audsys CLK_AUD_I2SO2>,
	<&topckgen CLK_TOP_ASM_M_SEL>,		<&audsys CLK_AUD_I2SO3>,
	<&topckgen CLK_TOP_ASM_H_SEL>,		<&audsys CLK_AUD_I2SO4>,
	<&topckgen CLK_TOP_UNIVPLL2_D4>,		<&audsys CLK_AUD_I2SIN1>,
	<&topckgen CLK_TOP_UNIVPLL2_D2>,		<&audsys CLK_AUD_I2SIN2>,
	<&topckgen CLK_TOP_SYSPLL_D5>;		<&audsys CLK_AUD_I2SIN3>,
			<&audsys CLK_AUD_I2SIN4>,
			<&audsys CLK_AUD_ASRCO1>,
			<&audsys CLK_AUD_ASRCO2>,
			<&audsys CLK_AUD_ASRCO3>,
			<&audsys CLK_AUD_ASRCO4>,
			<&audsys CLK_AUD_AFE>,
			<&audsys CLK_AUD_AFE_CONN>,
			<&audsys CLK_AUD_A1SYS>,
			<&audsys CLK_AUD_A2SYS>,
			<&audsys CLK_AUD_AFE_MRGIF>;

	clock-names = "infra_sys_audio_clk",		clock-names = "infra_sys_audio_clk",
	"top_audio_mux1_sel",		"top_audio_mux1_sel",
	"top_audio_mux2_sel",		"top_audio_mux2_sel",
	"top_audio_mux1_div",		"top_audio_a1sys_hp",
	"top_audio_mux2_div",		"top_audio_a2sys_hp",
	"top_audio_48k_timing",		"i2s0_src_sel",
	"top_audio_44k_timing",		"i2s1_src_sel",
	"top_audpll_mux_sel",		"i2s2_src_sel",
	"top_apll_sel",		"i2s3_src_sel",
	"top_aud1_pll_98M",		"i2s0_src_div",
	"top_aud2_pll_90M",		"i2s1_src_div",
	"top_hadds2_pll_98M",		"i2s2_src_div",
	"top_hadds2_pll_294M",		"i2s3_src_div",
	"top_audpll",		"i2s0_mclk_en",
	"top_audpll_d4",		"i2s1_mclk_en",
	"top_audpll_d8",		"i2s2_mclk_en",
	"top_audpll_d16",		"i2s3_mclk_en",
	"top_audpll_d24",		"i2so0_hop_ck",
	"top_audintbus_sel",		"i2so1_hop_ck",
	"clk_26m",		"i2so2_hop_ck",
	"top_syspll1_d4",		"i2so3_hop_ck",
	"top_aud_k1_src_sel",		"i2si0_hop_ck",
	"top_aud_k2_src_sel",		"i2si1_hop_ck",
	"top_aud_k3_src_sel",		"i2si2_hop_ck",
	"top_aud_k4_src_sel",		"i2si3_hop_ck",
	"top_aud_k5_src_sel",		"asrc0_out_ck",
	"top_aud_k6_src_sel",		"asrc1_out_ck",
	"top_aud_k1_src_div",		"asrc2_out_ck",
	"top_aud_k2_src_div",		"asrc3_out_ck",
	"top_aud_k3_src_div",		"audio_afe_pd",
	"top_aud_k4_src_div",		"audio_afe_conn_pd",
	"top_aud_k5_src_div",		"audio_a1sys_pd",
	"top_aud_k6_src_div",		"audio_a2sys_pd",
	"top_aud_i2s1_mclk",		"audio_mrgif_pd";
	"top_aud_i2s2_mclk",
	"top_aud_i2s3_mclk",		assigned-clocks = <&topckgen CLK_TOP_AUD_MUX1_SEL>,
	"top_aud_i2s4_mclk",		<&topckgen CLK_TOP_AUD_MUX2_SEL>,
	"top_aud_i2s5_mclk",		<&topckgen CLK_TOP_AUD_MUX1_DIV>,
	"top_aud_i2s6_mclk",		<&topckgen CLK_TOP_AUD_MUX2_DIV>;
	"top_asm_m_sel",		assigned-clock-parents = <&topckgen CLK_TOP_AUD1PLL_98M>,
	"top_asm_h_sel",		<&topckgen CLK_TOP_AUD2PLL_90M>;
	"top_univpll2_d4",		assigned-clock-rates = <0>, <0>, <49152000>, <45158400>;
	"top_univpll2_d2",		};
	"top_syspll_d5";
	};		};

sound/soc/codecs/max98927.c

+0 −1

Original line number	Original line	Diff line number	Diff line
	@@ -682,7 +682,6 @@ static int max98927_probe(struct snd_soc_codec *codec)
	struct max98927_priv *max98927 = snd_soc_codec_get_drvdata(codec);		struct max98927_priv *max98927 = snd_soc_codec_get_drvdata(codec);

	max98927->codec = codec;		max98927->codec = codec;
	codec->control_data = max98927->regmap;

	/* Software Reset */		/* Software Reset */
	regmap_write(max98927->regmap,		regmap_write(max98927->regmap,

sound/soc/codecs/mc13783.c

+3 −6

Original line number	Original line	Diff line number	Diff line
	@@ -610,6 +610,9 @@ static int mc13783_probe(struct snd_soc_codec *codec)
	{		{
	struct mc13783_priv *priv = snd_soc_codec_get_drvdata(codec);		struct mc13783_priv *priv = snd_soc_codec_get_drvdata(codec);

			snd_soc_codec_init_regmap(codec,
			dev_get_regmap(codec->dev->parent, NULL));

	/* these are the reset values */		/* these are the reset values */
	mc13xxx_reg_write(priv->mc13xxx, MC13783_AUDIO_RX0, 0x25893);		mc13xxx_reg_write(priv->mc13xxx, MC13783_AUDIO_RX0, 0x25893);
	mc13xxx_reg_write(priv->mc13xxx, MC13783_AUDIO_RX1, 0x00d35A);		mc13xxx_reg_write(priv->mc13xxx, MC13783_AUDIO_RX1, 0x00d35A);
	@@ -728,15 +731,9 @@ static struct snd_soc_dai_driver mc13783_dai_sync[] = {
	}		}
	};		};

	static struct regmap mc13783_get_regmap(struct device dev)
	{
	return dev_get_regmap(dev->parent, NULL);
	}

	static const struct snd_soc_codec_driver soc_codec_dev_mc13783 = {		static const struct snd_soc_codec_driver soc_codec_dev_mc13783 = {
	.probe = mc13783_probe,		.probe = mc13783_probe,
	.remove = mc13783_remove,		.remove = mc13783_remove,
	.get_regmap = mc13783_get_regmap,
	.component_driver = {		.component_driver = {
	.controls = mc13783_control_list,		.controls = mc13783_control_list,
	.num_controls = ARRAY_SIZE(mc13783_control_list),		.num_controls = ARRAY_SIZE(mc13783_control_list),

sound/soc/codecs/msm8916-wcd-analog.c

+2 −6

Original line number	Original line	Diff line number	Diff line
	@@ -712,6 +712,8 @@ static int pm8916_wcd_analog_probe(struct snd_soc_codec *codec)
	return err;		return err;
	}		}

			snd_soc_codec_init_regmap(codec,
			dev_get_regmap(codec->dev->parent, NULL));
	snd_soc_codec_set_drvdata(codec, priv);		snd_soc_codec_set_drvdata(codec, priv);
	priv->pmic_rev = snd_soc_read(codec, CDC_D_REVISION1);		priv->pmic_rev = snd_soc_read(codec, CDC_D_REVISION1);
	priv->codec_version = snd_soc_read(codec, CDC_D_PERPH_SUBTYPE);		priv->codec_version = snd_soc_read(codec, CDC_D_PERPH_SUBTYPE);
	@@ -943,11 +945,6 @@ static int pm8916_wcd_analog_set_jack(struct snd_soc_codec *codec,
	return 0;		return 0;
	}		}

	static struct regmap pm8916_get_regmap(struct device dev)
	{
	return dev_get_regmap(dev->parent, NULL);
	}

	static irqreturn_t mbhc_btn_release_irq_handler(int irq, void *arg)		static irqreturn_t mbhc_btn_release_irq_handler(int irq, void *arg)
	{		{
	struct pm8916_wcd_analog_priv *priv = arg;		struct pm8916_wcd_analog_priv *priv = arg;
	@@ -1082,7 +1079,6 @@ static const struct snd_soc_codec_driver pm8916_wcd_analog = {
	.probe = pm8916_wcd_analog_probe,		.probe = pm8916_wcd_analog_probe,
	.remove = pm8916_wcd_analog_remove,		.remove = pm8916_wcd_analog_remove,
	.set_jack = pm8916_wcd_analog_set_jack,		.set_jack = pm8916_wcd_analog_set_jack,
	.get_regmap = pm8916_get_regmap,
	.component_driver = {		.component_driver = {
	.controls = pm8916_wcd_analog_snd_controls,		.controls = pm8916_wcd_analog_snd_controls,
	.num_controls = ARRAY_SIZE(pm8916_wcd_analog_snd_controls),		.num_controls = ARRAY_SIZE(pm8916_wcd_analog_snd_controls),

sound/soc/mediatek/mt2701/mt2701-afe-clock-ctrl.c

+193 −359

File changed.

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