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Commit fa238712 authored by Yijing Wang's avatar Yijing Wang Committed by Bjorn Helgaas
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PCI: Document MPS parameters pci=pcie_bus_safe, pci=pcie_bus_perf, etc



Document PCIe bus MPS parameters pcie_bus_tune_off, pcie_bus_safe,
pcie_bus_peer2peer, pcie_bus_perf.

These parameters were introduced by Jon Mason <jdmason@kudzu.us> at commit
5f39e670 and commit b03e7495.

[bhelgaas: mention hot-add for pcie_bus_peer2peer]
Signed-off-by: default avatarYijing Wang <wangyijing@huawei.com>
Signed-off-by: default avatarBjorn Helgaas <bhelgaas@google.com>
parent 8c8803c5
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Original line number Diff line number Diff line
@@ -2227,6 +2227,21 @@ bytes respectively. Such letter suffixes can also be entirely omitted.
				This sorting is done to get a device
				order compatible with older (<= 2.4) kernels.
		nobfsort	Don't sort PCI devices into breadth-first order.
		pcie_bus_tune_off	Disable PCIe MPS (Max Payload Size)
				tuning and use the BIOS-configured MPS defaults.
		pcie_bus_safe	Set every device's MPS to the largest value
				supported by all devices below the root complex.
		pcie_bus_perf	Set device MPS to the largest allowable MPS
				based on its parent bus. Also set MRRS (Max
				Read Request Size) to the largest supported
				value (no larger than the MPS that the device
				or bus can support) for best performance.
		pcie_bus_peer2peer	Set every device's MPS to 128B, which
				every device is guaranteed to support. This
				configuration allows peer-to-peer DMA between
				any pair of devices, possibly at the cost of
				reduced performance.  This also guarantees
				that hot-added devices will work.
		cbiosize=nn[KMG]	The fixed amount of bus space which is
				reserved for the CardBus bridge's IO window.
				The default value is 256 bytes.