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Commit f9fc42f4 authored by Damien Lespiau's avatar Damien Lespiau Committed by Daniel Vetter
Browse files

drm/i915/skl: Implement WaDisableVFUnitClockGating 



Signed-off-by: default avatarDamien Lespiau <damien.lespiau@intel.com>
Reviewed-by: default avatarRodrigo Vivi <rodrigo.vivi@intel.com>
Signed-off-by: default avatarDaniel Vetter <daniel.vetter@ffwll.ch>
parent 669506e7

drivers/gpu/drm/i915/i915_reg.h

+1 −0
Original line number Diff line number Diff line
@@ -6102,6 +6102,7 @@ enum skl_disp_power_wells { 
# define GEN6_CSUNIT_CLOCK_GATE_DISABLE			(1 << 7)



#define GEN6_UCGCTL2				0x9404

# define GEN6_VFUNIT_CLOCK_GATE_DISABLE			(1 << 31)

# define GEN7_VDSUNIT_CLOCK_GATE_DISABLE		(1 << 30)

# define GEN7_TDLUNIT_CLOCK_GATE_DISABLE		(1 << 22)

# define GEN6_RCZUNIT_CLOCK_GATE_DISABLE		(1 << 13)

drivers/gpu/drm/i915/intel_pm.c

+4 −0
Original line number Diff line number Diff line
@@ -75,6 +75,10 @@ static void skl_init_clock_gating(struct drm_device *dev) 
		I915_WRITE(GEN8_UCGCTL6, I915_READ(GEN8_UCGCTL6) |

			   GEN8_GAPSUNIT_CLOCK_GATE_DISABLE |

			   GEN8_SDEUNIT_CLOCK_GATE_DISABLE);



		/* WaDisableVFUnitClockGating:skl */

		I915_WRITE(GEN6_UCGCTL2, I915_READ(GEN6_UCGCTL2) |

			   GEN6_VFUNIT_CLOCK_GATE_DISABLE);

	}



	if (INTEL_REVID(dev) <= SKL_REVID_D0) {