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Commit f9e7449c authored by Marc Zyngier's avatar Marc Zyngier
Browse files

KVM: arm64: vgic-v3: Add ICV_AP1Rn_EL1 handler 



Add a handler for reading/writing the guest's view of the ICV_AP1Rn_EL1
registers. We just map them to the corresponding ICH_AP1Rn_EL2 registers.

Tested-by: default avatarAlexander Graf <agraf@suse.de>
Acked-by: default avatarDavid Daney <david.daney@cavium.com>
Reviewed-by: default avatarEric Auger <eric.auger@redhat.com>
Reviewed-by: default avatarChristoffer Dall <cdall@linaro.org>
Signed-off-by: default avatarMarc Zyngier <marc.zyngier@arm.com>
Signed-off-by: default avatarChristoffer Dall <cdall@linaro.org>
parent b6f49035

arch/arm64/include/asm/sysreg.h

+1 −0
Original line number Diff line number Diff line
@@ -180,6 +180,7 @@ 


#define SYS_VBAR_EL1			sys_reg(3, 0, 12, 0, 0)



#define SYS_ICC_AP1Rn_EL1(n)		sys_reg(3, 0, 12, 9, n)

#define SYS_ICC_DIR_EL1			sys_reg(3, 0, 12, 11, 1)

#define SYS_ICC_SGI1R_EL1		sys_reg(3, 0, 12, 11, 5)

#define SYS_ICC_IAR1_EL1		sys_reg(3, 0, 12, 12, 0)

virt/kvm/arm/hyp/vgic-v3-sr.c

+94 −0
Original line number Diff line number Diff line
@@ -720,6 +720,76 @@ static void __hyp_text __vgic_v3_write_bpr1(struct kvm_vcpu *vcpu, u32 vmcr, int 
	__vgic_v3_write_vmcr(vmcr);

}



static void __hyp_text __vgic_v3_read_apxrn(struct kvm_vcpu *vcpu, int rt, int n)

{

	u32 val;



	if (!__vgic_v3_get_group(vcpu))

		val = __vgic_v3_read_ap0rn(n);

	else

		val = __vgic_v3_read_ap1rn(n);



	vcpu_set_reg(vcpu, rt, val);

}



static void __hyp_text __vgic_v3_write_apxrn(struct kvm_vcpu *vcpu, int rt, int n)

{

	u32 val = vcpu_get_reg(vcpu, rt);



	if (!__vgic_v3_get_group(vcpu))

		__vgic_v3_write_ap0rn(val, n);

	else

		__vgic_v3_write_ap1rn(val, n);

}



static void __hyp_text __vgic_v3_read_apxr0(struct kvm_vcpu *vcpu,

					    u32 vmcr, int rt)

{

	__vgic_v3_read_apxrn(vcpu, rt, 0);

}



static void __hyp_text __vgic_v3_read_apxr1(struct kvm_vcpu *vcpu,

					    u32 vmcr, int rt)

{

	__vgic_v3_read_apxrn(vcpu, rt, 1);

}



static void __hyp_text __vgic_v3_read_apxr2(struct kvm_vcpu *vcpu,

					    u32 vmcr, int rt)

{

	__vgic_v3_read_apxrn(vcpu, rt, 2);

}



static void __hyp_text __vgic_v3_read_apxr3(struct kvm_vcpu *vcpu,

					    u32 vmcr, int rt)

{

	__vgic_v3_read_apxrn(vcpu, rt, 3);

}



static void __hyp_text __vgic_v3_write_apxr0(struct kvm_vcpu *vcpu,

					     u32 vmcr, int rt)

{

	__vgic_v3_write_apxrn(vcpu, rt, 0);

}



static void __hyp_text __vgic_v3_write_apxr1(struct kvm_vcpu *vcpu,

					     u32 vmcr, int rt)

{

	__vgic_v3_write_apxrn(vcpu, rt, 1);

}



static void __hyp_text __vgic_v3_write_apxr2(struct kvm_vcpu *vcpu,

					     u32 vmcr, int rt)

{

	__vgic_v3_write_apxrn(vcpu, rt, 2);

}



static void __hyp_text __vgic_v3_write_apxr3(struct kvm_vcpu *vcpu,

					     u32 vmcr, int rt)

{

	__vgic_v3_write_apxrn(vcpu, rt, 3);

}



int __hyp_text __vgic_v3_perform_cpuif_access(struct kvm_vcpu *vcpu)

{

	int rt;
@@ -760,6 +830,30 @@ int __hyp_text __vgic_v3_perform_cpuif_access(struct kvm_vcpu *vcpu) 
		else

			fn = __vgic_v3_write_bpr1;

		break;

	case SYS_ICC_AP1Rn_EL1(0):

		if (is_read)

			fn = __vgic_v3_read_apxr0;

		else

			fn = __vgic_v3_write_apxr0;

		break;

	case SYS_ICC_AP1Rn_EL1(1):

		if (is_read)

			fn = __vgic_v3_read_apxr1;

		else

			fn = __vgic_v3_write_apxr1;

		break;

	case SYS_ICC_AP1Rn_EL1(2):

		if (is_read)

			fn = __vgic_v3_read_apxr2;

		else

			fn = __vgic_v3_write_apxr2;

		break;

	case SYS_ICC_AP1Rn_EL1(3):

		if (is_read)

			fn = __vgic_v3_read_apxr3;

		else

			fn = __vgic_v3_write_apxr3;

		break;

	default:

		return 0;

	}