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Commit f99c6bb6 authored by Linus Torvalds's avatar Linus Torvalds
Browse files

Merge master.kernel.org:/pub/scm/linux/kernel/git/lethal/sh-2.6 

* master.kernel.org:/pub/scm/linux/kernel/git/lethal/sh-2.6: (35 commits)
  sh: rts7751r2d board updates.
  sh: Kill off dead bigsur and ec3104 boards.
  sh: Fixup r7780rp pata_platform for devres conversion.
  sh: Revert TLB miss fast-path changes that broke PTEA parts.
  sh: Compile fix for heartbeat consolidation.
  sh: heartbeat consolidation for banked LEDs.
  sh: define dma noncoherent API functions.
  sh: Missing flush_dcache_all() proto in cacheflush.h.
  sh: Kill dead/unused ISA code from __ioremap().
  sh: Add cpu-features header to asm/Kbuild.
  sh: Move __KERNEL__ up in asm/page.h.
  sh: Fix syscall numbering breakage.
  sh: dcache write-back for R7780RP PIO.
  sh: Switch to local TLB flush variants in additional callsites.
  sh: Local TLB flushing variants for SMP prep.
  sh: Fixup cpu_data references for the non-boot CPUs.
  sh: Use a per-cpu ASID cache.
  sh: add SH_CLK_MD Kconfig default.
  sh: Fixup SHMIN INTC register definitions.
  sh: SH-DMAC compile fixes
  ...
parents e0a04cff 9c57548f

arch/sh/Kconfig

+6 −11
Original line number Diff line number Diff line
@@ -135,12 +135,6 @@ config SH_HP6XX 
	  More information (hardware only) at

	  <http://www.hp.com/jornada/>.



config SH_EC3104

	bool "EC3104"

	help

	  Select EC3104 if configuring for a system with an Eclipse

	  International EC3104 chip, e.g. the Harris AD2000.



config SH_SATURN

	bool "Saturn"

	select CPU_SUBTYPE_SH7604
@@ -156,9 +150,6 @@ config SH_DREAMCAST 
	  <http://www.m17n.org/linux-sh/dreamcast/>.  There is a

	  Dreamcast project is at <http://linuxdc.sourceforge.net/>.



config SH_BIGSUR

	bool "BigSur"



config SH_MPC1211

	bool "Interface MPC1211"

	help
@@ -481,6 +472,7 @@ config SH_PCLK_FREQ 


config SH_CLK_MD

	int "CPU Mode Pin Setting"

	default 0

	depends on CPU_SUBTYPE_SH7619 || CPU_SUBTYPE_SH7206

	help

	  MD2 - MD0 pin setting.
@@ -510,8 +502,9 @@ source "arch/sh/cchips/Kconfig" 
config HEARTBEAT

	bool "Heartbeat LED"

	depends on SH_MPC1211 || SH_SH03 || \

		   SH_BIGSUR || SOLUTION_ENGINE || \

		   SH_RTS7751R2D || SH_SH4202_MICRODEV || SH_LANDISK

		   SOLUTION_ENGINE || \

		   SH_RTS7751R2D || SH_SH4202_MICRODEV || SH_LANDISK || \

		   SH_R7780RP

	help

	  Use the power-on LED on your machine as a load meter.  The exact

	  behavior is platform-dependent, but normally the flash frequency is
@@ -596,6 +589,8 @@ menu "Boot options" 
config ZERO_PAGE_OFFSET

	hex "Zero page offset"

	default "0x00004000" if SH_MPC1211 || SH_SH03

	default "0x00010000" if PAGE_SIZE_64KB

	default "0x00002000" if PAGE_SIZE_8KB

	default "0x00001000"

	help

	  This sets the default offset of zero page.

arch/sh/Makefile

+1 −2
Original line number Diff line number Diff line
@@ -35,6 +35,7 @@ endif 
endif



cflags-$(CONFIG_CPU_SH2)		:= -m2

cflags-$(CONFIG_CPU_SH2A)		:= -m2a $(call cc-option,-m2a-nofpu,)

cflags-$(CONFIG_CPU_SH3)		:= -m3

cflags-$(CONFIG_CPU_SH4)		:= -m4 \

	$(call cc-option,-mno-implicit-fp,-m4-nofpu)
@@ -93,10 +94,8 @@ machdir-$(CONFIG_SH_7300_SOLUTION_ENGINE) := se/7300 
machdir-$(CONFIG_SH_7343_SOLUTION_ENGINE)	:= se/7343

machdir-$(CONFIG_SH_73180_SOLUTION_ENGINE)	:= se/73180

machdir-$(CONFIG_SH_HP6XX)			:= hp6xx

machdir-$(CONFIG_SH_EC3104)			:= ec3104

machdir-$(CONFIG_SH_SATURN)			:= saturn

machdir-$(CONFIG_SH_DREAMCAST)			:= dreamcast

machdir-$(CONFIG_SH_BIGSUR)			:= bigsur

machdir-$(CONFIG_SH_MPC1211)			:= mpc1211

machdir-$(CONFIG_SH_SH03)			:= sh03

machdir-$(CONFIG_SH_SECUREEDGE5410)		:= snapgear

arch/sh/boards/bigsur/Makefile

deleted100644 → 0
+0 −6
Original line number Diff line number Diff line 
#

# Makefile for the BigSur specific parts of the kernel

#



obj-y	 := setup.o io.o irq.o led.o

arch/sh/boards/bigsur/io.c

deleted100644 → 0
+0 −120
Original line number Diff line number Diff line 
/*

 * arch/sh/boards/bigsur/io.c

 *

 * By Dustin McIntire (dustin@sensoria.com) (c)2001

 * Derived from io_hd64465.h, which bore the message:

 * By Greg Banks <gbanks@pocketpenguins.com>

 * (c) 2000 PocketPenguins Inc. 

 * and from io_hd64461.h, which bore the message:

 * Copyright 2000 Stuart Menefy (stuart.menefy@st.com)

 *

 * May be copied or modified under the terms of the GNU General Public

 * License.  See linux/COPYING for more information.

 *

 * IO functions for a Hitachi Big Sur Evaluation Board.

 */



#include <linux/kernel.h>

#include <linux/module.h>

#include <asm/machvec.h>

#include <asm/io.h>

#include <asm/bigsur/bigsur.h>



/* Low iomap maps port 0-1K to addresses in 8byte chunks */

#define BIGSUR_IOMAP_LO_THRESH 0x400

#define BIGSUR_IOMAP_LO_SHIFT	3

#define BIGSUR_IOMAP_LO_MASK	((1<<BIGSUR_IOMAP_LO_SHIFT)-1)

#define BIGSUR_IOMAP_LO_NMAP	(BIGSUR_IOMAP_LO_THRESH>>BIGSUR_IOMAP_LO_SHIFT)

static u32 bigsur_iomap_lo[BIGSUR_IOMAP_LO_NMAP];

static u8 bigsur_iomap_lo_shift[BIGSUR_IOMAP_LO_NMAP];



/* High iomap maps port 1K-64K to addresses in 1K chunks */

#define BIGSUR_IOMAP_HI_THRESH 0x10000

#define BIGSUR_IOMAP_HI_SHIFT	10

#define BIGSUR_IOMAP_HI_MASK	((1<<BIGSUR_IOMAP_HI_SHIFT)-1)

#define BIGSUR_IOMAP_HI_NMAP	(BIGSUR_IOMAP_HI_THRESH>>BIGSUR_IOMAP_HI_SHIFT)

static u32 bigsur_iomap_hi[BIGSUR_IOMAP_HI_NMAP];

static u8 bigsur_iomap_hi_shift[BIGSUR_IOMAP_HI_NMAP];



void bigsur_port_map(u32 baseport, u32 nports, u32 addr, u8 shift)

{

	u32 port, endport = baseport + nports;



	pr_debug("bigsur_port_map(base=0x%0x, n=0x%0x, addr=0x%08x)\n",

		 baseport, nports, addr);

	    

	for (port = baseport ;

	     port < endport && port < BIGSUR_IOMAP_LO_THRESH ;

	     port += (1<<BIGSUR_IOMAP_LO_SHIFT)) {

	    	pr_debug("    maplo[0x%x] = 0x%08x\n", port, addr);

    	    bigsur_iomap_lo[port>>BIGSUR_IOMAP_LO_SHIFT] = addr;

    	    bigsur_iomap_lo_shift[port>>BIGSUR_IOMAP_LO_SHIFT] = shift;

	    	addr += (1<<(BIGSUR_IOMAP_LO_SHIFT));

	}



	for (port = max_t(u32, baseport, BIGSUR_IOMAP_LO_THRESH);

	     port < endport && port < BIGSUR_IOMAP_HI_THRESH ;

	     port += (1<<BIGSUR_IOMAP_HI_SHIFT)) {

	    	pr_debug("    maphi[0x%x] = 0x%08x\n", port, addr);

    	    bigsur_iomap_hi[port>>BIGSUR_IOMAP_HI_SHIFT] = addr;

    	    bigsur_iomap_hi_shift[port>>BIGSUR_IOMAP_HI_SHIFT] = shift;

	    	addr += (1<<(BIGSUR_IOMAP_HI_SHIFT));

	}

}

EXPORT_SYMBOL(bigsur_port_map);



void bigsur_port_unmap(u32 baseport, u32 nports)

{

	u32 port, endport = baseport + nports;

	

	pr_debug("bigsur_port_unmap(base=0x%0x, n=0x%0x)\n", baseport, nports);



	for (port = baseport ;

	     port < endport && port < BIGSUR_IOMAP_LO_THRESH ;

	     port += (1<<BIGSUR_IOMAP_LO_SHIFT)) {

		bigsur_iomap_lo[port>>BIGSUR_IOMAP_LO_SHIFT] = 0;

	}



	for (port = max_t(u32, baseport, BIGSUR_IOMAP_LO_THRESH);

	     port < endport && port < BIGSUR_IOMAP_HI_THRESH ;

	     port += (1<<BIGSUR_IOMAP_HI_SHIFT)) {

		bigsur_iomap_hi[port>>BIGSUR_IOMAP_HI_SHIFT] = 0;

	}

}

EXPORT_SYMBOL(bigsur_port_unmap);



unsigned long bigsur_isa_port2addr(unsigned long port)

{

	unsigned long addr = 0;

	unsigned char shift;



	/* Physical address not in P0, do nothing */

	if (PXSEG(port)) {

		addr = port;

	/* physical address in P0, map to P2 */

	} else if (port >= 0x30000) {

		addr = P2SEGADDR(port);

	/* Big Sur I/O + HD64465 registers 0x10000-0x30000 */

	} else if (port >= BIGSUR_IOMAP_HI_THRESH) {

		addr = BIGSUR_INTERNAL_BASE + (port - BIGSUR_IOMAP_HI_THRESH);

	/* Handle remapping of high IO/PCI IO ports */

	} else if (port >= BIGSUR_IOMAP_LO_THRESH) {

		addr = bigsur_iomap_hi[port >> BIGSUR_IOMAP_HI_SHIFT];

		shift = bigsur_iomap_hi_shift[port >> BIGSUR_IOMAP_HI_SHIFT];



		if (addr != 0)

			addr += (port & BIGSUR_IOMAP_HI_MASK) << shift;

	} else {

		/* Handle remapping of low IO ports */

		addr = bigsur_iomap_lo[port >> BIGSUR_IOMAP_LO_SHIFT];

		shift = bigsur_iomap_lo_shift[port >> BIGSUR_IOMAP_LO_SHIFT];



		if (addr != 0)

			addr += (port & BIGSUR_IOMAP_LO_MASK) << shift;

	}



	pr_debug("%s(0x%08lx) = 0x%08lx\n", __FUNCTION__, port, addr);



	return addr;

}

arch/sh/boards/bigsur/irq.c

deleted100644 → 0
+0 −334
Original line number Diff line number Diff line 
/*

 *

 * By Dustin McIntire (dustin@sensoria.com) (c)2001

 *

 * Setup and IRQ handling code for the HD64465 companion chip.

 * by Greg Banks <gbanks@pocketpenguins.com>

 * Copyright (c) 2000 PocketPenguins Inc

 *

 * Derived from setup_hd64465.c which bore the message:

 * Greg Banks <gbanks@pocketpenguins.com>

 * Copyright (c) 2000 PocketPenguins Inc and

 * Copyright (C) 2000 YAEGASHI Takeshi

 * and setup_cqreek.c which bore message:

 * Copyright (C) 2000  Niibe Yutaka

 *

 * May be copied or modified under the terms of the GNU General Public

 * License.  See linux/COPYING for more information.

 *

 * IRQ functions for a Hitachi Big Sur Evaluation Board.

 *

 */

#undef DEBUG



#include <linux/sched.h>

#include <linux/module.h>

#include <linux/kernel.h>

#include <linux/param.h>

#include <linux/ioport.h>

#include <linux/interrupt.h>

#include <linux/init.h>

#include <linux/irq.h>

#include <linux/bitops.h>



#include <asm/io.h>

#include <asm/irq.h>



#include <asm/bigsur/io.h>

#include <asm/hd64465/hd64465.h>

#include <asm/bigsur/bigsur.h>



//#define BIGSUR_DEBUG 3

#undef BIGSUR_DEBUG



#ifdef BIGSUR_DEBUG

#define DIPRINTK(n, args...)    if (BIGSUR_DEBUG>(n)) printk(args)

#else

#define DIPRINTK(n, args...)

#endif /* BIGSUR_DEBUG */



#ifdef CONFIG_HD64465

extern int hd64465_irq_demux(int irq);

#endif /* CONFIG_HD64465 */





/*===========================================================*/

//              Big Sur CPLD IRQ Routines

/*===========================================================*/



/* Level 1 IRQ routines */

static void disable_bigsur_l1irq(unsigned int irq)

{

        unsigned char mask;

        unsigned int mask_port = ((irq - BIGSUR_IRQ_LOW)/8) ? BIGSUR_IRLMR1 : BIGSUR_IRLMR0;

        unsigned char bit =  (1 << ((irq - MGATE_IRQ_LOW)%8) );



        if(irq >= BIGSUR_IRQ_LOW && irq < BIGSUR_IRQ_HIGH) {

                pr_debug("Disable L1 IRQ %d\n", irq);

                DIPRINTK(2,"disable_bigsur_l1irq: IMR=0x%08x mask=0x%x\n",

                        mask_port, bit);



                /* Disable IRQ - set mask bit */

                mask = inb(mask_port) | bit;

                outb(mask, mask_port);

                return;

        }

        pr_debug("disable_bigsur_l1irq: Invalid IRQ %d\n", irq);

}



static void enable_bigsur_l1irq(unsigned int irq)

{

        unsigned char mask;

        unsigned int mask_port = ((irq - BIGSUR_IRQ_LOW)/8) ? BIGSUR_IRLMR1 : BIGSUR_IRLMR0;

        unsigned char bit =  (1 << ((irq - MGATE_IRQ_LOW)%8) );



        if(irq >= BIGSUR_IRQ_LOW && irq < BIGSUR_IRQ_HIGH) {

                pr_debug("Enable L1 IRQ %d\n", irq);

                DIPRINTK(2,"enable_bigsur_l1irq: IMR=0x%08x mask=0x%x\n",

                        mask_port, bit);

                /* Enable L1 IRQ - clear mask bit */

                mask = inb(mask_port) & ~bit;

                outb(mask, mask_port);

                return;

        }

        pr_debug("enable_bigsur_l1irq: Invalid IRQ %d\n", irq);

}





/* Level 2 irq masks and registers for L2 decoding */

/* Level2 bitmasks for each level 1 IRQ */

const u32 bigsur_l2irq_mask[] =

    {0x40,0x80,0x08,0x01,0x01,0x3C,0x3E,0xFF,0x40,0x80,0x06,0x03};

/* Level2 to ISR[n] map for each level 1 IRQ */

const u32 bigsur_l2irq_reg[]  =

    {   2,   2,   3,   3,   1,   2,   1,   0,   1,   1,   3,   2};

/* Level2 to Level 1 IRQ map */

const u32 bigsur_l2_l1_map[]  =

    {7,7,7,7,7,7,7,7, 4,6,6,6,6,6,8,9, 11,11,5,5,5,5,0,1, 3,10,10,2,-1,-1,-1,-1};

/* IRQ inactive level (high or low) */

const u32 bigsur_l2_inactv_state[]  =   {0x00, 0xBE, 0xFC, 0xF7};



/* CPLD external status and mask registers base and offsets */

static const u32 isr_base = BIGSUR_IRQ0;

static const u32 isr_offset = BIGSUR_IRQ0 - BIGSUR_IRQ1;

static const u32 imr_base = BIGSUR_IMR0;

static const u32 imr_offset = BIGSUR_IMR0 - BIGSUR_IMR1;



#define REG_NUM(irq)  ((irq-BIGSUR_2NDLVL_IRQ_LOW)/8 )



/* Level 2 IRQ routines */

static void disable_bigsur_l2irq(unsigned int irq)

{

        unsigned char mask;

        unsigned char bit = 1 << ((irq-BIGSUR_2NDLVL_IRQ_LOW)%8);

        unsigned int mask_port = imr_base - REG_NUM(irq)*imr_offset;



	if(irq >= BIGSUR_2NDLVL_IRQ_LOW && irq < BIGSUR_2NDLVL_IRQ_HIGH) {

                pr_debug("Disable L2 IRQ %d\n", irq);

                DIPRINTK(2,"disable_bigsur_l2irq: IMR=0x%08x mask=0x%x\n",

                        mask_port, bit);



                /* Disable L2 IRQ - set mask bit */

                mask = inb(mask_port) | bit;

                outb(mask, mask_port);

                return;

        }

        pr_debug("disable_bigsur_l2irq: Invalid IRQ %d\n", irq);

}



static void enable_bigsur_l2irq(unsigned int irq)

{

        unsigned char mask;

        unsigned char bit = 1 << ((irq-BIGSUR_2NDLVL_IRQ_LOW)%8);

        unsigned int mask_port = imr_base - REG_NUM(irq)*imr_offset;



	if(irq >= BIGSUR_2NDLVL_IRQ_LOW && irq < BIGSUR_2NDLVL_IRQ_HIGH) {

                pr_debug("Enable L2 IRQ %d\n", irq);

                DIPRINTK(2,"enable_bigsur_l2irq: IMR=0x%08x mask=0x%x\n",

                        mask_port, bit);



                /* Enable L2 IRQ - clear mask bit */

                mask = inb(mask_port) & ~bit;

                outb(mask, mask_port);

                return;

        }

        pr_debug("enable_bigsur_l2irq: Invalid IRQ %d\n", irq);

}



static void mask_and_ack_bigsur(unsigned int irq)

{

        pr_debug("mask_and_ack_bigsur IRQ %d\n", irq);

        if(irq >= BIGSUR_IRQ_LOW && irq < BIGSUR_IRQ_HIGH)

                disable_bigsur_l1irq(irq);

        else

                disable_bigsur_l2irq(irq);

}



static void end_bigsur_irq(unsigned int irq)

{

        pr_debug("end_bigsur_irq IRQ %d\n", irq);

        if (!(irq_desc[irq].status & (IRQ_DISABLED|IRQ_INPROGRESS))) {

                if(irq >= BIGSUR_IRQ_LOW && irq < BIGSUR_IRQ_HIGH)

                        enable_bigsur_l1irq(irq);

                else

                        enable_bigsur_l2irq(irq);

        }

}



static unsigned int startup_bigsur_irq(unsigned int irq)

{

        u8 mask;

        u32 reg;



        pr_debug("startup_bigsur_irq IRQ %d\n", irq);



        if(irq >= BIGSUR_IRQ_LOW && irq < BIGSUR_IRQ_HIGH) {

                /* Enable the L1 IRQ */

                enable_bigsur_l1irq(irq);

                /* Enable all L2 IRQs in this L1 IRQ */

                mask = ~(bigsur_l2irq_mask[irq-BIGSUR_IRQ_LOW]);

                reg = imr_base - bigsur_l2irq_reg[irq-BIGSUR_IRQ_LOW] * imr_offset;

                mask &= inb(reg);

                outb(mask,reg);

                DIPRINTK(2,"startup_bigsur_irq: IMR=0x%08x mask=0x%x\n",reg,inb(reg));

        }

        else {

                /* Enable the L2 IRQ - clear mask bit */

                enable_bigsur_l2irq(irq);

                /* Enable the L1 bit masking this L2 IRQ */

                enable_bigsur_l1irq(bigsur_l2_l1_map[irq-BIGSUR_2NDLVL_IRQ_LOW]);

                DIPRINTK(2,"startup_bigsur_irq: L1=%d L2=%d\n",

                        bigsur_l2_l1_map[irq-BIGSUR_2NDLVL_IRQ_LOW],irq);

        }

        return 0;

}



static void shutdown_bigsur_irq(unsigned int irq)

{

        pr_debug("shutdown_bigsur_irq IRQ %d\n", irq);

        if(irq >= BIGSUR_IRQ_LOW && irq < BIGSUR_IRQ_HIGH)

                disable_bigsur_l1irq(irq);

        else

                disable_bigsur_l2irq(irq);

}



/* Define the IRQ structures for the L1 and L2 IRQ types */

static struct hw_interrupt_type bigsur_l1irq_type = {

	.typename  = "BigSur-CPLD-Level1-IRQ",

	.startup = startup_bigsur_irq,

	.shutdown = shutdown_bigsur_irq,

	.enable = enable_bigsur_l1irq,

	.disable = disable_bigsur_l1irq,

	.ack = mask_and_ack_bigsur,

	.end = end_bigsur_irq

};



static struct hw_interrupt_type bigsur_l2irq_type = {

	.typename  = "BigSur-CPLD-Level2-IRQ",

	.startup = startup_bigsur_irq,

	.shutdown  =shutdown_bigsur_irq,

	.enable = enable_bigsur_l2irq,

	.disable = disable_bigsur_l2irq,

	.ack = mask_and_ack_bigsur,

	.end = end_bigsur_irq

};





static void make_bigsur_l1isr(unsigned int irq) {



        /* sanity check first */

        if(irq >= BIGSUR_IRQ_LOW && irq < BIGSUR_IRQ_HIGH) {

                /* save the handler in the main description table */

                irq_desc[irq].chip = &bigsur_l1irq_type;

                irq_desc[irq].status = IRQ_DISABLED;

                irq_desc[irq].action = 0;

                irq_desc[irq].depth = 1;



                disable_bigsur_l1irq(irq);

                return;

        }

        pr_debug("make_bigsur_l1isr: bad irq, %d\n", irq);

        return;

}



static void make_bigsur_l2isr(unsigned int irq) {



        /* sanity check first */

        if(irq >= BIGSUR_2NDLVL_IRQ_LOW && irq < BIGSUR_2NDLVL_IRQ_HIGH) {

                /* save the handler in the main description table */

                irq_desc[irq].chip = &bigsur_l2irq_type;

                irq_desc[irq].status = IRQ_DISABLED;

                irq_desc[irq].action = 0;

                irq_desc[irq].depth = 1;



                disable_bigsur_l2irq(irq);

                return;

        }

        pr_debug("make_bigsur_l2isr: bad irq, %d\n", irq);

        return;

}



/* The IRQ's will be decoded as follows:

 * If a level 2 handler exists and there is an unmasked active

 * IRQ, the 2nd level handler will be called.

 * If a level 2 handler does not exist for the active IRQ

 * the 1st level handler will be called.

 */



int bigsur_irq_demux(int irq)

{

        int dmux_irq = irq;

        u8 mask, actv_irqs;

        u32 reg_num;



        DIPRINTK(3,"bigsur_irq_demux, irq=%d\n", irq);

        /* decode the 1st level IRQ */

        if(irq >= BIGSUR_IRQ_LOW && irq < BIGSUR_IRQ_HIGH) {

                /* Get corresponding L2 ISR bitmask and ISR number */

                mask = bigsur_l2irq_mask[irq-BIGSUR_IRQ_LOW];

                reg_num = bigsur_l2irq_reg[irq-BIGSUR_IRQ_LOW];

                /* find the active IRQ's (XOR with inactive level)*/

                actv_irqs = inb(isr_base-reg_num*isr_offset) ^

                                        bigsur_l2_inactv_state[reg_num];

                /* decode active IRQ's */

                actv_irqs = actv_irqs & mask & ~(inb(imr_base-reg_num*imr_offset));

                /* if NEZ then we have an active L2 IRQ */

                if(actv_irqs) dmux_irq = ffz(~actv_irqs) + reg_num*8+BIGSUR_2NDLVL_IRQ_LOW;

                /* if no 2nd level IRQ action, but has 1st level, use 1st level handler */

                if(!irq_desc[dmux_irq].action && irq_desc[irq].action)

                        dmux_irq = irq;

                DIPRINTK(1,"bigsur_irq_demux: irq=%d dmux_irq=%d mask=0x%04x reg=%d\n",

                        irq, dmux_irq, mask, reg_num);

        }

#ifdef CONFIG_HD64465

        dmux_irq = hd64465_irq_demux(dmux_irq);

#endif /* CONFIG_HD64465 */

        DIPRINTK(3,"bigsur_irq_demux, demux_irq=%d\n", dmux_irq);



        return dmux_irq;

}



/*===========================================================*/

//              Big Sur Init Routines

/*===========================================================*/

void __init init_bigsur_IRQ(void)

{

        int i;



        if (!MACH_BIGSUR) return;



        /* Create ISR's for Big Sur CPLD IRQ's */

        /*==============================================================*/

        for(i=BIGSUR_IRQ_LOW;i<BIGSUR_IRQ_HIGH;i++)

                make_bigsur_l1isr(i);



        printk(KERN_INFO "Big Sur CPLD L1 interrupts %d to %d.\n",

                BIGSUR_IRQ_LOW,BIGSUR_IRQ_HIGH);



        for(i=BIGSUR_2NDLVL_IRQ_LOW;i<BIGSUR_2NDLVL_IRQ_HIGH;i++)

                make_bigsur_l2isr(i);



        printk(KERN_INFO "Big Sur CPLD L2 interrupts %d to %d.\n",

                BIGSUR_2NDLVL_IRQ_LOW,BIGSUR_2NDLVL_IRQ_HIGH);



}