Loading drivers/ide/sl82c105.c +1 −23 Original line number Diff line number Diff line Loading @@ -24,13 +24,6 @@ #define DRV_NAME "sl82c105" #undef DEBUG #ifdef DEBUG #define DBG(arg) printk arg #else #define DBG(fmt,...) #endif /* * SL82C105 PCI config register 0x40 bits. */ Loading Loading @@ -104,9 +97,6 @@ static void sl82c105_set_dma_mode(ide_drive_t *drive, const u8 speed) unsigned long timings = (unsigned long)ide_get_drivedata(drive); u16 drv_ctrl; DBG(("sl82c105_tune_chipset(drive:%s, speed:%s)\n", drive->name, ide_xfer_verbose(speed))); drv_ctrl = mwdma_timings[speed - XFER_MW_DMA_0]; /* Loading Loading @@ -196,8 +186,6 @@ static void sl82c105_dma_start(ide_drive_t *drive) struct pci_dev *dev = to_pci_dev(hwif->dev); int reg = 0x44 + drive->dn * 4; DBG(("%s(drive:%s)\n", __func__, drive->name)); pci_write_config_word(dev, reg, (unsigned long)ide_get_drivedata(drive) >> 16); Loading @@ -209,8 +197,6 @@ static void sl82c105_dma_clear(ide_drive_t *drive) { struct pci_dev *dev = to_pci_dev(drive->hwif->dev); DBG(("sl82c105_dma_clear(drive:%s)\n", drive->name)); sl82c105_reset_host(dev); } Loading @@ -218,11 +204,7 @@ static int sl82c105_dma_end(ide_drive_t *drive) { struct pci_dev *dev = to_pci_dev(drive->hwif->dev); int reg = 0x44 + drive->dn * 4; int ret; DBG(("%s(drive:%s)\n", __func__, drive->name)); ret = ide_dma_end(drive); int ret = ide_dma_end(drive); pci_write_config_word(dev, reg, (unsigned long)ide_get_drivedata(drive)); Loading @@ -239,8 +221,6 @@ static void sl82c105_resetproc(ide_drive_t *drive) struct pci_dev *dev = to_pci_dev(drive->hwif->dev); u32 val; DBG(("sl82c105_resetproc(drive:%s)\n", drive->name)); pci_read_config_dword(dev, 0x40, &val); val |= (CTRL_P1F16 | CTRL_P0F16); pci_write_config_dword(dev, 0x40, val); Loading Loading @@ -291,8 +271,6 @@ static int init_chipset_sl82c105(struct pci_dev *dev) { u32 val; DBG(("init_chipset_sl82c105()\n")); pci_read_config_dword(dev, 0x40, &val); val |= CTRL_P0EN | CTRL_P0F16 | CTRL_P1F16; pci_write_config_dword(dev, 0x40, val); Loading Loading
drivers/ide/sl82c105.c +1 −23 Original line number Diff line number Diff line Loading @@ -24,13 +24,6 @@ #define DRV_NAME "sl82c105" #undef DEBUG #ifdef DEBUG #define DBG(arg) printk arg #else #define DBG(fmt,...) #endif /* * SL82C105 PCI config register 0x40 bits. */ Loading Loading @@ -104,9 +97,6 @@ static void sl82c105_set_dma_mode(ide_drive_t *drive, const u8 speed) unsigned long timings = (unsigned long)ide_get_drivedata(drive); u16 drv_ctrl; DBG(("sl82c105_tune_chipset(drive:%s, speed:%s)\n", drive->name, ide_xfer_verbose(speed))); drv_ctrl = mwdma_timings[speed - XFER_MW_DMA_0]; /* Loading Loading @@ -196,8 +186,6 @@ static void sl82c105_dma_start(ide_drive_t *drive) struct pci_dev *dev = to_pci_dev(hwif->dev); int reg = 0x44 + drive->dn * 4; DBG(("%s(drive:%s)\n", __func__, drive->name)); pci_write_config_word(dev, reg, (unsigned long)ide_get_drivedata(drive) >> 16); Loading @@ -209,8 +197,6 @@ static void sl82c105_dma_clear(ide_drive_t *drive) { struct pci_dev *dev = to_pci_dev(drive->hwif->dev); DBG(("sl82c105_dma_clear(drive:%s)\n", drive->name)); sl82c105_reset_host(dev); } Loading @@ -218,11 +204,7 @@ static int sl82c105_dma_end(ide_drive_t *drive) { struct pci_dev *dev = to_pci_dev(drive->hwif->dev); int reg = 0x44 + drive->dn * 4; int ret; DBG(("%s(drive:%s)\n", __func__, drive->name)); ret = ide_dma_end(drive); int ret = ide_dma_end(drive); pci_write_config_word(dev, reg, (unsigned long)ide_get_drivedata(drive)); Loading @@ -239,8 +221,6 @@ static void sl82c105_resetproc(ide_drive_t *drive) struct pci_dev *dev = to_pci_dev(drive->hwif->dev); u32 val; DBG(("sl82c105_resetproc(drive:%s)\n", drive->name)); pci_read_config_dword(dev, 0x40, &val); val |= (CTRL_P1F16 | CTRL_P0F16); pci_write_config_dword(dev, 0x40, val); Loading Loading @@ -291,8 +271,6 @@ static int init_chipset_sl82c105(struct pci_dev *dev) { u32 val; DBG(("init_chipset_sl82c105()\n")); pci_read_config_dword(dev, 0x40, &val); val |= CTRL_P0EN | CTRL_P0F16 | CTRL_P1F16; pci_write_config_dword(dev, 0x40, val); Loading