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Commit f861a925 authored by Gerhard Sittig's avatar Gerhard Sittig Committed by Brian Norris
Browse files

devicetree: bindings: improve description for GPIO assisted NAND flash 



Expand the description of the 'gpios' property in the GPIO assisted
NAND flash binding, to explicitly list the required GPIO pin references
and their order.

Update the example section to individually bracket the GPIO references,
and capitalize the signal names for improved readability.

Signed-off-by: default avatarGerhard Sittig <gsi@denx.de>
Signed-off-by: default avatarBrian Norris <computersforpeace@gmail.com>
parent 1f04a73e

Documentation/devicetree/bindings/mtd/gpio-control-nand.txt

+7 −7
Original line number Diff line number Diff line
@@ -11,8 +11,8 @@ Required properties: 
  are made in native endianness.

- #address-cells, #size-cells : Must be present if the device has sub-nodes

  representing partitions.

- gpios : specifies the gpio pins to control the NAND device.  nwp is an

  optional gpio and may be set to 0 if not present.

- gpios : Specifies the GPIO pins to control the NAND device.  The order of

  GPIO references is:  RDY, nCE, ALE, CLE, and an optional nWP.



Optional properties:

- bank-width : Width (in bytes) of the device.  If not present, the width
@@ -35,11 +35,11 @@ gpio-nand@1,0 { 
	reg = <1 0x0000 0x2>;

	#address-cells = <1>;

	#size-cells = <1>;

	gpios = <&banka 1 0	/* rdy */

		 &banka 2 0 	/* nce */

		 &banka 3 0 	/* ale */

		 &banka 4 0 	/* cle */

		 0		/* nwp */>;

	gpios = <&banka 1 0>,	/* RDY */

		<&banka 2 0>, 	/* nCE */

		<&banka 3 0>, 	/* ALE */

		<&banka 4 0>, 	/* CLE */

		<0>;		/* nWP */



	partition@0 {

	...