Commit f81a3487 authored Nov 21, 2017 by Mark Rutland Committed by Will Deacon Nov 28, 2017

arm64: mm: cleanup stale AIVIVT references



Since commit:

  155433cb ("arm64: cache: Remove support for ASID-tagged VIVT I-caches")

... the kernel no longer cares about AIVIVT I-caches, as these were
removed from the architecture.

This patch removes the stale references to such I-caches.

The comment in flush_context() is also updated to clarify when and where
the TLB invalidation occurs.

Signed-off-by: Mark Rutland <mark.rutland@arm.com>
Cc: Catalin Marinas <catalin.marinas@arm.com>
Cc: Will Deacon <will.deacon@arm.com>
Signed-off-by: Will Deacon <will.deacon@arm.com>

parent 4fbd8d19

arch/arm64/include/asm/cacheflush.h

+1 −1

Original line number	Diff line number	Diff line
		@@ -38,7 +38,7 @@
		*
		* See Documentation/cachetlb.txt for more information. Please note that
		* the implementation assumes non-aliasing VIPT D-cache and (aliasing)
		* VIPT or ASID-tagged VIVT I-cache.
		* VIPT I-cache.
		*
		* flush_cache_mm(mm)
		*

arch/arm64/mm/context.c

+4 −1

Original line number	Diff line number	Diff line
		@@ -117,7 +117,10 @@ static void flush_context(unsigned int cpu)
		per_cpu(reserved_asids, i) = asid;
		}

		/* Queue a TLB invalidate and flush the I-cache if necessary. */
		/*
		* Queue a TLB invalidation for each CPU to perform on next
		* context-switch
		*/
		cpumask_setall(&tlb_flush_pending);
		}