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Commit f7cf78b9 authored by Linus Walleij's avatar Linus Walleij
Browse files

Merge tag 'sh-pfc-for-v4.10-tag1' of... 

Merge tag 'sh-pfc-for-v4.10-tag1' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-drivers into devel

pinctrl: sh-pfc: Updates for v4.10

  - I2C and DRIF pin groups for R-Car M3-W,
  - Bug fixes for SDHI2/3 on R-Car M3-W.
parents fc669d13 0f866a96

drivers/pinctrl/sh-pfc/pfc-r8a7796.c

+378 −10
Original line number Diff line number Diff line
@@ -122,22 +122,22 @@ 
#define GPSR3_0		F_(SD0_CLK,		IP7_19_16)



/* GPSR4 */

#define GPSR4_17	F_(SD3_DS,		IP11_11_8)

#define GPSR4_16	F_(SD3_DAT7,		IP10_7_4)

#define GPSR4_15	F_(SD3_DAT6,		IP10_3_0)

#define GPSR4_14	F_(SD3_DAT5,		IP9_31_28)

#define GPSR4_13	F_(SD3_DAT4,		IP9_27_24)

#define GPSR4_17	F_(SD3_DS,		IP11_7_4)

#define GPSR4_16	F_(SD3_DAT7,		IP11_3_0)

#define GPSR4_15	F_(SD3_DAT6,		IP10_31_28)

#define GPSR4_14	F_(SD3_DAT5,		IP10_27_24)

#define GPSR4_13	F_(SD3_DAT4,		IP10_23_20)

#define GPSR4_12	F_(SD3_DAT3,		IP10_19_16)

#define GPSR4_11	F_(SD3_DAT2,		IP10_15_12)

#define GPSR4_10	F_(SD3_DAT1,		IP10_11_8)

#define GPSR4_9		F_(SD3_DAT0,		IP10_7_4)

#define GPSR4_8		F_(SD3_CMD,		IP10_3_0)

#define GPSR4_7		F_(SD3_CLK,		IP9_31_28)

#define GPSR4_6		F_(SD2_DS,		IP9_23_20)

#define GPSR4_5		F_(SD2_DAT3,		IP9_19_16)

#define GPSR4_4		F_(SD2_DAT2,		IP9_15_12)

#define GPSR4_3		F_(SD2_DAT1,		IP9_11_8)

#define GPSR4_2		F_(SD2_DAT0,		IP9_7_4)

#define GPSR4_6		F_(SD2_DS,		IP9_27_24)

#define GPSR4_5		F_(SD2_DAT3,		IP9_23_20)

#define GPSR4_4		F_(SD2_DAT2,		IP9_19_16)

#define GPSR4_3		F_(SD2_DAT1,		IP9_15_12)

#define GPSR4_2		F_(SD2_DAT0,		IP9_11_8)

#define GPSR4_1		F_(SD2_CMD,		IP9_7_4)

#define GPSR4_0		F_(SD2_CLK,		IP9_3_0)
@@ -1490,6 +1490,272 @@ static const struct sh_pfc_pin pinmux_pins[] = { 
	PINMUX_GPIO_GP_ALL(),

};



/* - DRIF0 --------------------------------------------------------------- */

static const unsigned int drif0_ctrl_a_pins[] = {

	/* CLK, SYNC */

	RCAR_GP_PIN(6, 8), RCAR_GP_PIN(6, 9),

};

static const unsigned int drif0_ctrl_a_mux[] = {

	RIF0_CLK_A_MARK, RIF0_SYNC_A_MARK,

};

static const unsigned int drif0_data0_a_pins[] = {

	/* D0 */

	RCAR_GP_PIN(6, 10),

};

static const unsigned int drif0_data0_a_mux[] = {

	RIF0_D0_A_MARK,

};

static const unsigned int drif0_data1_a_pins[] = {

	/* D1 */

	RCAR_GP_PIN(6, 7),

};

static const unsigned int drif0_data1_a_mux[] = {

	RIF0_D1_A_MARK,

};

static const unsigned int drif0_ctrl_b_pins[] = {

	/* CLK, SYNC */

	RCAR_GP_PIN(5, 0), RCAR_GP_PIN(5, 4),

};

static const unsigned int drif0_ctrl_b_mux[] = {

	RIF0_CLK_B_MARK, RIF0_SYNC_B_MARK,

};

static const unsigned int drif0_data0_b_pins[] = {

	/* D0 */

	RCAR_GP_PIN(5, 1),

};

static const unsigned int drif0_data0_b_mux[] = {

	RIF0_D0_B_MARK,

};

static const unsigned int drif0_data1_b_pins[] = {

	/* D1 */

	RCAR_GP_PIN(5, 2),

};

static const unsigned int drif0_data1_b_mux[] = {

	RIF0_D1_B_MARK,

};

static const unsigned int drif0_ctrl_c_pins[] = {

	/* CLK, SYNC */

	RCAR_GP_PIN(5, 12), RCAR_GP_PIN(5, 15),

};

static const unsigned int drif0_ctrl_c_mux[] = {

	RIF0_CLK_C_MARK, RIF0_SYNC_C_MARK,

};

static const unsigned int drif0_data0_c_pins[] = {

	/* D0 */

	RCAR_GP_PIN(5, 13),

};

static const unsigned int drif0_data0_c_mux[] = {

	RIF0_D0_C_MARK,

};

static const unsigned int drif0_data1_c_pins[] = {

	/* D1 */

	RCAR_GP_PIN(5, 14),

};

static const unsigned int drif0_data1_c_mux[] = {

	RIF0_D1_C_MARK,

};

/* - DRIF1 --------------------------------------------------------------- */

static const unsigned int drif1_ctrl_a_pins[] = {

	/* CLK, SYNC */

	RCAR_GP_PIN(6, 17), RCAR_GP_PIN(6, 18),

};

static const unsigned int drif1_ctrl_a_mux[] = {

	RIF1_CLK_A_MARK, RIF1_SYNC_A_MARK,

};

static const unsigned int drif1_data0_a_pins[] = {

	/* D0 */

	RCAR_GP_PIN(6, 19),

};

static const unsigned int drif1_data0_a_mux[] = {

	RIF1_D0_A_MARK,

};

static const unsigned int drif1_data1_a_pins[] = {

	/* D1 */

	RCAR_GP_PIN(6, 20),

};

static const unsigned int drif1_data1_a_mux[] = {

	RIF1_D1_A_MARK,

};

static const unsigned int drif1_ctrl_b_pins[] = {

	/* CLK, SYNC */

	RCAR_GP_PIN(5, 9), RCAR_GP_PIN(5, 3),

};

static const unsigned int drif1_ctrl_b_mux[] = {

	RIF1_CLK_B_MARK, RIF1_SYNC_B_MARK,

};

static const unsigned int drif1_data0_b_pins[] = {

	/* D0 */

	RCAR_GP_PIN(5, 7),

};

static const unsigned int drif1_data0_b_mux[] = {

	RIF1_D0_B_MARK,

};

static const unsigned int drif1_data1_b_pins[] = {

	/* D1 */

	RCAR_GP_PIN(5, 8),

};

static const unsigned int drif1_data1_b_mux[] = {

	RIF1_D1_B_MARK,

};

static const unsigned int drif1_ctrl_c_pins[] = {

	/* CLK, SYNC */

	RCAR_GP_PIN(5, 5), RCAR_GP_PIN(5, 11),

};

static const unsigned int drif1_ctrl_c_mux[] = {

	RIF1_CLK_C_MARK, RIF1_SYNC_C_MARK,

};

static const unsigned int drif1_data0_c_pins[] = {

	/* D0 */

	RCAR_GP_PIN(5, 6),

};

static const unsigned int drif1_data0_c_mux[] = {

	RIF1_D0_C_MARK,

};

static const unsigned int drif1_data1_c_pins[] = {

	/* D1 */

	RCAR_GP_PIN(5, 10),

};

static const unsigned int drif1_data1_c_mux[] = {

	RIF1_D1_C_MARK,

};

/* - DRIF2 --------------------------------------------------------------- */

static const unsigned int drif2_ctrl_a_pins[] = {

	/* CLK, SYNC */

	RCAR_GP_PIN(6, 8), RCAR_GP_PIN(6, 9),

};

static const unsigned int drif2_ctrl_a_mux[] = {

	RIF2_CLK_A_MARK, RIF2_SYNC_A_MARK,

};

static const unsigned int drif2_data0_a_pins[] = {

	/* D0 */

	RCAR_GP_PIN(6, 7),

};

static const unsigned int drif2_data0_a_mux[] = {

	RIF2_D0_A_MARK,

};

static const unsigned int drif2_data1_a_pins[] = {

	/* D1 */

	RCAR_GP_PIN(6, 10),

};

static const unsigned int drif2_data1_a_mux[] = {

	RIF2_D1_A_MARK,

};

static const unsigned int drif2_ctrl_b_pins[] = {

	/* CLK, SYNC */

	RCAR_GP_PIN(6, 26), RCAR_GP_PIN(6, 27),

};

static const unsigned int drif2_ctrl_b_mux[] = {

	RIF2_CLK_B_MARK, RIF2_SYNC_B_MARK,

};

static const unsigned int drif2_data0_b_pins[] = {

	/* D0 */

	RCAR_GP_PIN(6, 30),

};

static const unsigned int drif2_data0_b_mux[] = {

	RIF2_D0_B_MARK,

};

static const unsigned int drif2_data1_b_pins[] = {

	/* D1 */

	RCAR_GP_PIN(6, 31),

};

static const unsigned int drif2_data1_b_mux[] = {

	RIF2_D1_B_MARK,

};

/* - DRIF3 --------------------------------------------------------------- */

static const unsigned int drif3_ctrl_a_pins[] = {

	/* CLK, SYNC */

	RCAR_GP_PIN(6, 17), RCAR_GP_PIN(6, 18),

};

static const unsigned int drif3_ctrl_a_mux[] = {

	RIF3_CLK_A_MARK, RIF3_SYNC_A_MARK,

};

static const unsigned int drif3_data0_a_pins[] = {

	/* D0 */

	RCAR_GP_PIN(6, 19),

};

static const unsigned int drif3_data0_a_mux[] = {

	RIF3_D0_A_MARK,

};

static const unsigned int drif3_data1_a_pins[] = {

	/* D1 */

	RCAR_GP_PIN(6, 20),

};

static const unsigned int drif3_data1_a_mux[] = {

	RIF3_D1_A_MARK,

};

static const unsigned int drif3_ctrl_b_pins[] = {

	/* CLK, SYNC */

	RCAR_GP_PIN(6, 24), RCAR_GP_PIN(6, 25),

};

static const unsigned int drif3_ctrl_b_mux[] = {

	RIF3_CLK_B_MARK, RIF3_SYNC_B_MARK,

};

static const unsigned int drif3_data0_b_pins[] = {

	/* D0 */

	RCAR_GP_PIN(6, 28),

};

static const unsigned int drif3_data0_b_mux[] = {

	RIF3_D0_B_MARK,

};

static const unsigned int drif3_data1_b_pins[] = {

	/* D1 */

	RCAR_GP_PIN(6, 29),

};

static const unsigned int drif3_data1_b_mux[] = {

	RIF3_D1_B_MARK,

};



/* - I2C -------------------------------------------------------------------- */

static const unsigned int i2c1_a_pins[] = {

	/* SDA, SCL */

	RCAR_GP_PIN(5, 11), RCAR_GP_PIN(5, 10),

};

static const unsigned int i2c1_a_mux[] = {

	SDA1_A_MARK, SCL1_A_MARK,

};

static const unsigned int i2c1_b_pins[] = {

	/* SDA, SCL */

	RCAR_GP_PIN(5, 24), RCAR_GP_PIN(5, 23),

};

static const unsigned int i2c1_b_mux[] = {

	SDA1_B_MARK, SCL1_B_MARK,

};

static const unsigned int i2c2_a_pins[] = {

	/* SDA, SCL */

	RCAR_GP_PIN(5, 0), RCAR_GP_PIN(5, 4),

};

static const unsigned int i2c2_a_mux[] = {

	SDA2_A_MARK, SCL2_A_MARK,

};

static const unsigned int i2c2_b_pins[] = {

	/* SDA, SCL */

	RCAR_GP_PIN(3, 13), RCAR_GP_PIN(3, 12),

};

static const unsigned int i2c2_b_mux[] = {

	SDA2_B_MARK, SCL2_B_MARK,

};

static const unsigned int i2c6_a_pins[] = {

	/* SDA, SCL */

	RCAR_GP_PIN(1, 8), RCAR_GP_PIN(1, 11),

};

static const unsigned int i2c6_a_mux[] = {

	SDA6_A_MARK, SCL6_A_MARK,

};

static const unsigned int i2c6_b_pins[] = {

	/* SDA, SCL */

	RCAR_GP_PIN(1, 26), RCAR_GP_PIN(1, 25),

};

static const unsigned int i2c6_b_mux[] = {

	SDA6_B_MARK, SCL6_B_MARK,

};

static const unsigned int i2c6_c_pins[] = {

	/* SDA, SCL */

	RCAR_GP_PIN(0, 15), RCAR_GP_PIN(0, 14),

};

static const unsigned int i2c6_c_mux[] = {

	SDA6_C_MARK, SCL6_C_MARK,

};



/* - SCIF0 ------------------------------------------------------------------ */

static const unsigned int scif0_data_pins[] = {

	/* RX, TX */
@@ -1912,6 +2178,43 @@ static const unsigned int sdhi3_ds_mux[] = { 
};



static const struct sh_pfc_pin_group pinmux_groups[] = {

	SH_PFC_PIN_GROUP(drif0_ctrl_a),

	SH_PFC_PIN_GROUP(drif0_data0_a),

	SH_PFC_PIN_GROUP(drif0_data1_a),

	SH_PFC_PIN_GROUP(drif0_ctrl_b),

	SH_PFC_PIN_GROUP(drif0_data0_b),

	SH_PFC_PIN_GROUP(drif0_data1_b),

	SH_PFC_PIN_GROUP(drif0_ctrl_c),

	SH_PFC_PIN_GROUP(drif0_data0_c),

	SH_PFC_PIN_GROUP(drif0_data1_c),

	SH_PFC_PIN_GROUP(drif1_ctrl_a),

	SH_PFC_PIN_GROUP(drif1_data0_a),

	SH_PFC_PIN_GROUP(drif1_data1_a),

	SH_PFC_PIN_GROUP(drif1_ctrl_b),

	SH_PFC_PIN_GROUP(drif1_data0_b),

	SH_PFC_PIN_GROUP(drif1_data1_b),

	SH_PFC_PIN_GROUP(drif1_ctrl_c),

	SH_PFC_PIN_GROUP(drif1_data0_c),

	SH_PFC_PIN_GROUP(drif1_data1_c),

	SH_PFC_PIN_GROUP(drif2_ctrl_a),

	SH_PFC_PIN_GROUP(drif2_data0_a),

	SH_PFC_PIN_GROUP(drif2_data1_a),

	SH_PFC_PIN_GROUP(drif2_ctrl_b),

	SH_PFC_PIN_GROUP(drif2_data0_b),

	SH_PFC_PIN_GROUP(drif2_data1_b),

	SH_PFC_PIN_GROUP(drif3_ctrl_a),

	SH_PFC_PIN_GROUP(drif3_data0_a),

	SH_PFC_PIN_GROUP(drif3_data1_a),

	SH_PFC_PIN_GROUP(drif3_ctrl_b),

	SH_PFC_PIN_GROUP(drif3_data0_b),

	SH_PFC_PIN_GROUP(drif3_data1_b),

	SH_PFC_PIN_GROUP(i2c1_a),

	SH_PFC_PIN_GROUP(i2c1_b),

	SH_PFC_PIN_GROUP(i2c2_a),

	SH_PFC_PIN_GROUP(i2c2_b),

	SH_PFC_PIN_GROUP(i2c6_a),

	SH_PFC_PIN_GROUP(i2c6_b),

	SH_PFC_PIN_GROUP(i2c6_c),

	SH_PFC_PIN_GROUP(scif0_data),

	SH_PFC_PIN_GROUP(scif0_clk),

	SH_PFC_PIN_GROUP(scif0_ctrl),
@@ -1969,6 +2272,64 @@ static const struct sh_pfc_pin_group pinmux_groups[] = { 
	SH_PFC_PIN_GROUP(sdhi3_ds),

};



static const char * const drif0_groups[] = {

	"drif0_ctrl_a",

	"drif0_data0_a",

	"drif0_data1_a",

	"drif0_ctrl_b",

	"drif0_data0_b",

	"drif0_data1_b",

	"drif0_ctrl_c",

	"drif0_data0_c",

	"drif0_data1_c",

};



static const char * const drif1_groups[] = {

	"drif1_ctrl_a",

	"drif1_data0_a",

	"drif1_data1_a",

	"drif1_ctrl_b",

	"drif1_data0_b",

	"drif1_data1_b",

	"drif1_ctrl_c",

	"drif1_data0_c",

	"drif1_data1_c",

};



static const char * const drif2_groups[] = {

	"drif2_ctrl_a",

	"drif2_data0_a",

	"drif2_data1_a",

	"drif2_ctrl_b",

	"drif2_data0_b",

	"drif2_data1_b",

};



static const char * const drif3_groups[] = {

	"drif3_ctrl_a",

	"drif3_data0_a",

	"drif3_data1_a",

	"drif3_ctrl_b",

	"drif3_data0_b",

	"drif3_data1_b",

};



static const char * const i2c1_groups[] = {

	"i2c1_a",

	"i2c1_b",

};



static const char * const i2c2_groups[] = {

	"i2c2_a",

	"i2c2_b",

};



static const char * const i2c6_groups[] = {

	"i2c6_a",

	"i2c6_b",

	"i2c6_c",

};



static const char * const scif0_groups[] = {

	"scif0_data",

	"scif0_clk",
@@ -2058,6 +2419,13 @@ static const char * const sdhi3_groups[] = { 
};



static const struct sh_pfc_function pinmux_functions[] = {

	SH_PFC_FUNCTION(drif0),

	SH_PFC_FUNCTION(drif1),

	SH_PFC_FUNCTION(drif2),

	SH_PFC_FUNCTION(drif3),

	SH_PFC_FUNCTION(i2c1),

	SH_PFC_FUNCTION(i2c2),

	SH_PFC_FUNCTION(i2c6),

	SH_PFC_FUNCTION(scif0),

	SH_PFC_FUNCTION(scif1),

	SH_PFC_FUNCTION(scif2),