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Commit f779b3e5 authored by Alex Deucher's avatar Alex Deucher Committed by Dave Airlie
Browse files

drm/radeon: add GET_PARAM/INFO support for Z pipes 



Needed for occlusion queries on rv530 chips.

Signed-off-by: default avatarAlex Deucher <alexdeucher@gmail.com>
Signed-off-by: default avatarDave Airlie <airlied@redhat.com>
parent 17782d99

drivers/gpu/drm/radeon/r300.c

+3 −1
Original line number Diff line number Diff line
@@ -448,6 +448,7 @@ void r300_gpu_init(struct radeon_device *rdev) 
		/* rv350,rv370,rv380 */

		rdev->num_gb_pipes = 1;

	}

	rdev->num_z_pipes = 1;

	gb_tile_config = (R300_ENABLE_TILING | R300_TILE_SIZE_16);

	switch (rdev->num_gb_pipes) {

	case 2:
@@ -486,7 +487,8 @@ void r300_gpu_init(struct radeon_device *rdev) 
		printk(KERN_WARNING "Failed to wait MC idle while "

		       "programming pipes. Bad things might happen.\n");

	}

	DRM_INFO("radeon: %d pipes initialized.\n", rdev->num_gb_pipes);

	DRM_INFO("radeon: %d quad pipes, %d Z pipes initialized.\n",

		 rdev->num_gb_pipes, rdev->num_z_pipes);

}



int r300_ga_reset(struct radeon_device *rdev)

drivers/gpu/drm/radeon/r420.c

+12 −1
Original line number Diff line number Diff line
@@ -165,7 +165,18 @@ void r420_pipes_init(struct radeon_device *rdev) 
		printk(KERN_WARNING "Failed to wait GUI idle while "

		       "programming pipes. Bad things might happen.\n");

	}

	DRM_INFO("radeon: %d pipes initialized.\n", rdev->num_gb_pipes);



	if (rdev->family == CHIP_RV530) {

		tmp = RREG32(RV530_GB_PIPE_SELECT2);

		if ((tmp & 3) == 3)

			rdev->num_z_pipes = 2;

		else

			rdev->num_z_pipes = 1;

	} else

		rdev->num_z_pipes = 1;



	DRM_INFO("radeon: %d quad pipes, %d z pipes initialized.\n",

		 rdev->num_gb_pipes, rdev->num_z_pipes);

}



void r420_gpu_init(struct radeon_device *rdev)

drivers/gpu/drm/radeon/r520.c

+0 −1
Original line number Diff line number Diff line
@@ -177,7 +177,6 @@ void r520_gpu_init(struct radeon_device *rdev) 
	 */

	/* workaround for RV530 */

	if (rdev->family == CHIP_RV530) {

		WREG32(0x4124, 1);

		WREG32(0x4128, 0xFF);

	}

	r420_pipes_init(rdev);

drivers/gpu/drm/radeon/radeon.h

+1 −0
Original line number Diff line number Diff line
@@ -655,6 +655,7 @@ struct radeon_device { 
	int				usec_timeout;

	enum radeon_pll_errata		pll_errata;

	int				num_gb_pipes;

	int				num_z_pipes;

	int				disp_priority;

	/* BIOS */

	uint8_t				*bios;

drivers/gpu/drm/radeon/radeon_cp.c

+9 −0
Original line number Diff line number Diff line
@@ -406,6 +406,15 @@ static void radeon_init_pipes(drm_radeon_private_t *dev_priv) 
{

	uint32_t gb_tile_config, gb_pipe_sel = 0;



	if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV530) {

		uint32_t z_pipe_sel = RADEON_READ(RV530_GB_PIPE_SELECT2);

		if ((z_pipe_sel & 3) == 3)

			dev_priv->num_z_pipes = 2;

		else

			dev_priv->num_z_pipes = 1;

	} else

		dev_priv->num_z_pipes = 1;



	/* RS4xx/RS6xx/R4xx/R5xx */

	if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R420) {

		gb_pipe_sel = RADEON_READ(R400_GB_PIPE_SELECT);