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Commit f6a681e0 authored by Alan Cox's avatar Alan Cox Committed by Greg Kroah-Hartman
Browse files

atomisp: HRT_CSIM is never defined 



Remove the content that is guarded by this define

Signed-off-by: default avatarAlan Cox <alan@linux.intel.com>
Signed-off-by: default avatarGreg Kroah-Hartman <gregkh@linuxfoundation.org>
parent e35d4427

drivers/staging/media/atomisp/pci/atomisp2/css2400/hive_isp_css_common/host/input_formatter.c

+0 −7
Original line number Diff line number Diff line
@@ -204,15 +204,8 @@ void input_formatter_bin_get_state( 
	assert(ID < N_INPUT_FORMATTER_ID);

	assert(state != NULL);



#ifdef HRT_CSIM

	/* The compiled simulator mode of the input formatter

	 * does not support reading from the write-only reset

	 * register. */

	state->reset = 0;

#else

	state->reset = input_formatter_reg_load(ID,

		HIVE_STR2MEM_SOFT_RESET_REG_ADDRESS);

#endif

	state->input_endianness = input_formatter_reg_load(ID,

		HIVE_STR2MEM_INPUT_ENDIANNESS_REG_ADDRESS);

	state->output_endianness = input_formatter_reg_load(ID,

drivers/staging/media/atomisp/pci/atomisp2/css2400/hive_isp_css_common/host/irq.c

+2 −9
Original line number Diff line number Diff line
@@ -218,9 +218,6 @@ void irq_raise( 
/* The SW IRQ pins are remapped to offset zero */

	gp_device_reg_store(GP_DEVICE0_ID,

		(unsigned int)addr, 1);

#ifdef HRT_CSIM

	hrt_sleep();

#endif

	gp_device_reg_store(GP_DEVICE0_ID,

		(unsigned int)addr, 0);

return;
@@ -416,10 +413,6 @@ assert(ID < N_IRQ_ID); 
	assert(IRQ_BASE[ID] != (hrt_address)-1);

	(void)ia_css_device_load_uint32(IRQ_BASE[ID] +

		_HRT_IRQ_CONTROLLER_ENABLE_REG_IDX*sizeof(hrt_data));

#ifdef HRT_CSIM

	hrt_sleep();

#endif

return;

}



STORAGE_CLASS_INLINE bool any_irq_channel_enabled(

drivers/staging/media/atomisp/pci/atomisp2/css2400/runtime/debug/src/ia_css_debug.c

+0 −16
Original line number Diff line number Diff line
@@ -2578,29 +2578,13 @@ ia_css_debug_mode_enable_dma_channel(int dma_id, 
void dtrace_dot(const char *fmt, ...)

{

	va_list ap;

#ifdef HRT_CSIM

	va_list ap2;

#endif



	assert(fmt != NULL);

	va_start(ap, fmt);

#ifdef HRT_CSIM

	va_start(ap2, fmt);

#endif



	ia_css_debug_dtrace(IA_CSS_DEBUG_INFO, "%s", DPG_START);

	ia_css_debug_vdtrace(IA_CSS_DEBUG_INFO, fmt, ap);

	ia_css_debug_dtrace(IA_CSS_DEBUG_INFO, "%s", DPG_END);

#ifdef HRT_CSIM

	/* For CSIM we print double because HSS log can mess up this output

	 * As post processing, we remove incomplete lines and make lines uniq.

	 * */

	ia_css_debug_dtrace(IA_CSS_DEBUG_INFO, "%s", DPG_START);

	ia_css_debug_vdtrace(IA_CSS_DEBUG_INFO, fmt, ap2);

	ia_css_debug_dtrace(IA_CSS_DEBUG_INFO, "%s", DPG_END);\



	va_end(ap2);

#endif

	va_end(ap);

}

#ifdef HAS_WATCHDOG_SP_THREAD_DEBUG

drivers/staging/media/atomisp/pci/atomisp2/css2400/runtime/spctrl/src/spctrl.c

+2 −83
Original line number Diff line number Diff line
@@ -32,10 +32,6 @@ more details. 
#define __INLINE_SP__

#include "sp.h"



#ifdef HRT_CSIM

#include <hive_isp_css_sp_hrt.h>

#endif



#include "memory_access.h"

#include "assert_support.h"

#include "ia_css_spctrl.h"
@@ -113,28 +109,11 @@ enum ia_css_err ia_css_spctrl_load_fw(sp_ID_t sp_id, 
	spctrl_cofig_info[sp_id].code_addr = code_addr;

	spctrl_cofig_info[sp_id].program_name = spctrl_cfg->program_name;



#ifdef HRT_CSIM

	/* Secondary SP is named as SP2 in SDK, however we are using secondary

	   SP as SP1 in the HSS and secondary SP Firmware */

	if (sp_id == SP0_ID) {

		hrt_cell_set_icache_base_address(SP, spctrl_cofig_info[sp_id].code_addr);

		hrt_cell_invalidate_icache(SP);

		hrt_cell_load_program(SP, spctrl_cofig_info[sp_id].program_name);

	}

#if defined(HAS_SEC_SP)

	else {

		hrt_cell_set_icache_base_address(SP2, spctrl_cofig_info[sp_id].code_addr);

		hrt_cell_invalidate_icache(SP2);

		hrt_cell_load_program(SP2, spctrl_cofig_info[sp_id].program_name);

	}

#endif /* HAS_SEC_SP */

#else

	/* now we program the base address into the icache and

	 * invalidate the cache.

	 */

	sp_ctrl_store(sp_id, SP_ICACHE_ADDR_REG, (hrt_data)spctrl_cofig_info[sp_id].code_addr);

	sp_ctrl_setbit(sp_id, SP_ICACHE_INV_REG, SP_ICACHE_INV_BIT);

#endif

	spctrl_loaded[sp_id] = true;

	return IA_CSS_SUCCESS;

}
@@ -143,32 +122,15 @@ enum ia_css_err ia_css_spctrl_load_fw(sp_ID_t sp_id, 
/* reload pre-loaded FW */

void sh_css_spctrl_reload_fw(sp_ID_t sp_id)

{

#ifdef HRT_CSIM

	/* Secondary SP is named as SP2 in SDK, however we are using secondary

	SP as SP1 in the HSS and secondary SP Firmware */

	if (sp_id == SP0_ID) {

		hrt_cell_set_icache_base_address(SP, spctrl_cofig_info[sp_id].code_addr);

		hrt_cell_invalidate_icache(SP);

		hrt_cell_load_program(SP, spctrl_cofig_info[sp_id].program_name);

	}

#if defined(HAS_SEC_SP)

	else {

		hrt_cell_set_icache_base_address(SP2, spctrl_cofig_info[sp_id].code_addr);

		hrt_cell_invalidate_icache(SP2);

		hrt_cell_load_program(SP2, spctrl_cofig_info[sp_id].program_name);

	}

#endif /* HAS_SEC_SP */

#else

	/* now we program the base address into the icache and

	* invalidate the cache.

	*/

	sp_ctrl_store(sp_id, SP_ICACHE_ADDR_REG, (hrt_data)spctrl_cofig_info[sp_id].code_addr);

	sp_ctrl_setbit(sp_id, SP_ICACHE_INV_REG, SP_ICACHE_INV_BIT);

#endif

	spctrl_loaded[sp_id] = true;

}



#endif



hrt_vaddress get_sp_code_addr(sp_ID_t  sp_id)

{

	return spctrl_cofig_info[sp_id].code_addr;
@@ -186,40 +148,6 @@ enum ia_css_err ia_css_spctrl_unload_fw(sp_ID_t sp_id) 
	return IA_CSS_SUCCESS;

}



#ifdef HRT_CSIM

enum ia_css_err ia_css_spctrl_start(sp_ID_t sp_id)

{

	unsigned int HIVE_ADDR_sp_start_isp_entry;

#if defined(HAS_SEC_SP)

	unsigned int HIVE_ADDR_sp1_start_entry;

#endif /* HAS_SEC_SP */

	if ((sp_id >= N_SP_ID) || ((sp_id < N_SP_ID) && (!spctrl_loaded[sp_id])))

		return IA_CSS_ERR_INVALID_ARGUMENTS;

if (sp_id == SP0_ID)

	HIVE_ADDR_sp_start_isp_entry = spctrl_cofig_info[sp_id].sp_entry;

#if defined(HAS_SEC_SP)

else

	HIVE_ADDR_sp1_start_entry = spctrl_cofig_info[sp_id].sp_entry;

#endif /* HAS_SEC_SP  */



#if !defined(C_RUN) && !defined(HRT_UNSCHED)

	sp_dmem_store(sp_id,

		spctrl_cofig_info[sp_id].spctrl_config_dmem_addr,

		&spctrl_cofig_info[sp_id].dmem_config,

		sizeof(spctrl_cofig_info[sp_id].dmem_config));

#endif

	if (sp_id == SP0_ID)

		hrt_cell_start_function(SP, sp_start_isp);

#if defined(HAS_SEC_SP)

	else

		/* Secondary SP is named as sp1 in the firmware however in

		   SDK secondary SP is named as SP2 */

		hrt_cell_start_function(SP2, sp1_start);

#endif /* HAS_SEC_SP */



	return IA_CSS_SUCCESS;

}

#else

/* Initialize dmem_cfg in SP dmem  and  start SP program*/

enum ia_css_err ia_css_spctrl_start(sp_ID_t sp_id)

{
@@ -244,7 +172,7 @@ enum ia_css_err ia_css_spctrl_start(sp_ID_t sp_id) 
	sp_ctrl_setbit(sp_id, SP_SC_REG, SP_START_BIT);

	return IA_CSS_SUCCESS;

}

#endif



/* Query the state of SP1 */

ia_css_spctrl_sp_sw_state ia_css_spctrl_get_state(sp_ID_t sp_id)

{
@@ -270,16 +198,7 @@ int ia_css_spctrl_is_idle(sp_ID_t sp_id) 
	int state = 0;

	assert (sp_id < N_SP_ID);



#ifdef HRT_CSIM

	if (sp_id == SP0_ID)

		state = (int)hrt_ctl_is_ready(SP);

#if defined(HAS_SEC_SP)

	else

		state = (int)hrt_ctl_is_ready(SP2);

#endif /* HAS_SEC_SP */

#else /* HRT_CSIM */

	state = sp_ctrl_getbit(sp_id, SP_SC_REG, SP_IDLE_BIT);

#endif /* HRT_CSIM */

	return state;

}

drivers/staging/media/atomisp/pci/atomisp2/css2400/sh_css.c

+0 −42
Original line number Diff line number Diff line
@@ -1575,14 +1575,6 @@ enable_interrupts(enum ia_css_irq_type irq_type) 
		ia_css_isys_rx_enable_all_interrupts(port);

#endif



#if defined(HRT_CSIM)

	/*

	 * Enable IRQ on the SP which signals that SP goes to idle

	 * to get statistics for each binary

	 */

	cnd_isp_irq_enable(ISP0_ID, true);

	cnd_virq_enable_channel(virq_isp, true);

#endif

	IA_CSS_LEAVE_PRIVATE("");

}
@@ -1939,18 +1931,6 @@ ia_css_init(const struct ia_css_env *env, 
	}

#endif /* HAS_BL */



#if defined(HRT_CSIM)

	/**

	 * In compiled simulator context include debug support by default.

	 * In all other cases (e.g. Android phone), the user (e.g. driver)

	 * must explicitly enable debug support by calling this function.

	 */

	if (!ia_css_debug_mode_init()) {

		IA_CSS_LEAVE_ERR(IA_CSS_ERR_INTERNAL_ERROR);

		return IA_CSS_ERR_INTERNAL_ERROR;

	}

#endif



#if WITH_PC_MONITORING

	if (!thread_alive) {

		thread_alive++;
@@ -2317,10 +2297,6 @@ create_host_pipeline(struct ia_css_stream *stream) 
				goto ERR;

		}



#ifdef HRT_CSIM

		if(main_pipe->continuous_frames[0])

			ia_css_frame_zero(main_pipe->continuous_frames[0]);

#endif

	}



#if defined(USE_INPUT_SYSTEM_VERSION_2)
@@ -2806,11 +2782,6 @@ enum ia_css_err ia_css_irq_translate( 
			infos |= IA_CSS_IRQ_INFO_EVENTS_READY;

			break;

		case virq_isp:

#ifdef HRT_CSIM

			/* Enable IRQ which signals that ISP goes to idle

			 * to get statistics for each binary */

			infos |= IA_CSS_IRQ_INFO_ISP_BINARY_STATISTICS_READY;

#endif

			break;

#if !defined(HAS_NO_INPUT_SYSTEM)

		case virq_isys_sof:
@@ -6062,9 +6033,6 @@ static enum ia_css_err load_video_binaries(struct ia_css_pipe *pipe) 
		err = ia_css_frame_allocate_from_info(

				&mycs->tnr_frames[i],

				&tnr_info);

#ifdef HRT_CSIM

		ia_css_frame_zero(mycs->tnr_frames[i]);

#endif

		if (err != IA_CSS_SUCCESS)

			return err;

	}
@@ -6773,9 +6741,6 @@ allocate_delay_frames(struct ia_css_pipe *pipe) 
		err = ia_css_frame_allocate_from_info(&delay_frames[i],	&ref_info);

		if (err != IA_CSS_SUCCESS)

			return err;

#if defined(HRT_CSIM) || defined(__SVOS__)

		ia_css_frame_zero(delay_frames[i]);

#endif

	}

	IA_CSS_LEAVE_PRIVATE("");

	return IA_CSS_SUCCESS;
@@ -11193,10 +11158,8 @@ enum ia_css_err 
ia_css_pipe_update_qos_ext_mapped_arg(struct ia_css_pipe *pipe, uint32_t fw_handle,

	struct ia_css_isp_param_css_segments *css_seg, struct ia_css_isp_param_isp_segments *isp_seg)

{

#ifndef HRT_CSIM

	unsigned int HIVE_ADDR_sp_group;

	static struct sh_css_sp_group sp_group;

#endif

	static struct sh_css_sp_stage sp_stage;

	static struct sh_css_isp_stage isp_stage;

	const struct ia_css_fw_info *fw;
@@ -11235,17 +11198,12 @@ ia_css_pipe_update_qos_ext_mapped_arg(struct ia_css_pipe *pipe, uint32_t fw_hand 
			} else {

				stage_num = stage->stage_num;



#ifndef HRT_CSIM

				HIVE_ADDR_sp_group = fw->info.sp.group;

				sp_dmem_load(SP0_ID,

					(unsigned int)sp_address_of(sp_group),

					&sp_group, sizeof(struct sh_css_sp_group));

				mmgr_load(sp_group.pipe[thread_id].sp_stage_addr[stage_num],

					&sp_stage, sizeof(struct sh_css_sp_stage));

#else

				mmgr_load(sh_css_sp_group.pipe[thread_id].sp_stage_addr[stage_num],

					&sp_stage, sizeof(struct sh_css_sp_stage));

#endif



				mmgr_load(sp_stage.isp_stage_addr,

					&isp_stage, sizeof(struct sh_css_isp_stage));