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Commit f66fab8e authored by Ville Syrjälä's avatar Ville Syrjälä Committed by Daniel Vetter
Browse files

drm/i915: Prevent MI_DISPLAY_FLIP straddling two cachelines on IVB 

According to BSpec the entire MI_DISPLAY_FLIP packet must be contained
in a single cacheline. Make sure that happens.

v2: Use intel_ring_begin_cacheline_safe()
v3: Use intel_ring_cacheline_align() (Chris)

Cc: Bjoern C <lkml@call-home.ch>
Cc: Alexandru DAMIAN <alexandru.damian@intel.com>
Cc: Enrico Tagliavini <enrico.tagliavini@gmail.com>
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=74053


Signed-off-by: default avatarVille Syrjälä <ville.syrjala@linux.intel.com>
Cc: stable@vger.kernel.org
Signed-off-by: default avatarDaniel Vetter <daniel.vetter@ffwll.ch>
parent 753b1ad4

drivers/gpu/drm/i915/intel_display.c

+14 −0
Original line number Original line Diff line number Diff line
@@ -8586,6 +8586,20 @@ static int intel_gen7_queue_flip(struct drm_device *dev, 
	if (ring->id == RCS)

	if (ring->id == RCS)

		len += 6;

		len += 6;





	/*

	 * BSpec MI_DISPLAY_FLIP for IVB:

	 * "The full packet must be contained within the same cache line."

	 *

	 * Currently the LRI+SRM+MI_DISPLAY_FLIP all fit within the same

	 * cacheline, if we ever start emitting more commands before

	 * the MI_DISPLAY_FLIP we may need to first emit everything else,

	 * then do the cacheline alignment, and finally emit the

	 * MI_DISPLAY_FLIP.

	 */

	ret = intel_ring_cacheline_align(ring);

	if (ret)

		goto err_unpin;



	ret = intel_ring_begin(ring, len);

	ret = intel_ring_begin(ring, len);

	if (ret)

	if (ret)

		goto err_unpin;

		goto err_unpin;