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Unverified Commit f609cc3a authored by Matt Redfearn's avatar Matt Redfearn Committed by James Hogan
Browse files

MIPS: Watch: Avoid duplication of bits in mips_install_watch_registers. 



Currently the bits to be set in the watchhi register in addition to that
requested by the user is defined inline for each register. To avoid
this, define the bits once and or that in for each register.

Signed-off-by: default avatarMatt Redfearn <matt.redfearn@mips.com>
Acked-by: default avatarDavid Daney <david.daney@cavium.com>
Reviewed-by: default avatarJames Hogan <jhogan@kernel.org>
Cc: Ralf Baechle <ralf@linux-mips.org>
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/18157/


Signed-off-by: default avatarJames Hogan <jhogan@kernel.org>
parent 93738d48

arch/mips/kernel/watch.c

+7 −10
Original line number Diff line number Diff line
@@ -18,27 +18,24 @@ 
void mips_install_watch_registers(struct task_struct *t)

{

	struct mips3264_watch_reg_state *watches = &t->thread.watch.mips3264;

	unsigned int watchhi = MIPS_WATCHHI_G |		/* Trap all ASIDs */

			       MIPS_WATCHHI_IRW;	/* Clear result bits */



	switch (current_cpu_data.watch_reg_use_cnt) {

	default:

		BUG();

	case 4:

		write_c0_watchlo3(watches->watchlo[3]);

		/* Write 1 to the I, R, and W bits to clear them, and

		   1 to G so all ASIDs are trapped. */

		write_c0_watchhi3(MIPS_WATCHHI_G | MIPS_WATCHHI_IRW |

				  watches->watchhi[3]);

		write_c0_watchhi3(watchhi | watches->watchhi[3]);

	case 3:

		write_c0_watchlo2(watches->watchlo[2]);

		write_c0_watchhi2(MIPS_WATCHHI_G | MIPS_WATCHHI_IRW |

				  watches->watchhi[2]);

		write_c0_watchhi2(watchhi | watches->watchhi[2]);

	case 2:

		write_c0_watchlo1(watches->watchlo[1]);

		write_c0_watchhi1(MIPS_WATCHHI_G | MIPS_WATCHHI_IRW |

				  watches->watchhi[1]);

		write_c0_watchhi1(watchhi | watches->watchhi[1]);

	case 1:

		write_c0_watchlo0(watches->watchlo[0]);

		write_c0_watchhi0(MIPS_WATCHHI_G | MIPS_WATCHHI_IRW |

				  watches->watchhi[0]);

		write_c0_watchhi0(watchhi | watches->watchhi[0]);

	}

}