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Commit f5959cb0 authored by Vineet Gupta's avatar Vineet Gupta
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Revert "ARCv2: STAR 9000837815 workaround hardware exclusive transactions livelock" 



Extended testing of quad core configuration revealed that this fix was
insufficient. Specifically LTP open posix shm_op/23-1 would cause the
hardware livelock in llock/scond loop in update_cpu_load_active()

So remove this and make way for a proper workaround

This reverts commit a5c8b52a.

Signed-off-by: default avatarVineet Gupta <vgupta@synopsys.com>
parent 6de7abfb

arch/arc/include/asm/atomic.h

+2 −12
Original line number Diff line number Diff line
@@ -23,21 +23,13 @@ 


#define atomic_set(v, i) (((v)->counter) = (i))



#ifdef CONFIG_ISA_ARCV2

#define PREFETCHW	"	prefetchw   [%1]	\n"

#else

#define PREFETCHW

#endif



#define ATOMIC_OP(op, c_op, asm_op)					\

static inline void atomic_##op(int i, atomic_t *v)			\

{									\

	unsigned int temp;						\

									\

	__asm__ __volatile__(						\

	"1:				\n"				\

	PREFETCHW							\

	"	llock   %0, [%1]	\n"				\

	"1:	llock   %0, [%1]	\n"				\

	"	" #asm_op " %0, %0, %2	\n"				\

	"	scond   %0, [%1]	\n"				\

	"	bnz     1b		\n"				\
@@ -58,9 +50,7 @@ static inline int atomic_##op##_return(int i, atomic_t *v) \ 
	smp_mb();							\

									\

	__asm__ __volatile__(						\

	"1:				\n"				\

	PREFETCHW							\

	"	llock   %0, [%1]	\n"				\

	"1:	llock   %0, [%1]	\n"				\

	"	" #asm_op " %0, %0, %2	\n"				\

	"	scond   %0, [%1]	\n"				\

	"	bnz     1b		\n"				\