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Commit f5590134 authored by Dave Airlie's avatar Dave Airlie
Browse files

Merge branch 'msm-next' of git://people.freedesktop.org/~robclark/linux into drm-next 

On the userspace side, all the basics are working, and most of glmark2
is working.  I've been working through deqp, and I've got a couple more
things to fix (but we've gone from 70% to 80+% pass in last day, and
current deqp run that is going should pick up another 5-10%).  I expect
to push the mesa patches today or tomorrow.

There are a couple more a5xx related patches to take the gpu out of
secure mode (for the devices that come up in secure mode, like the hw
I have), but those depend on an scm patch that would come in through
another tree.  If that can land in the next day or two, there might
be a second late pull request for drm/msm.

In addition to the new-shiny, there have also been a lot of overlay/
plane related fixes for issues found using drm-hwc2 (in the process of
testing/debugging the atomic/kms fence patches), resulting in rework
to assign hwpipes to kms planes dynamically (as part of global atomic
state) and also handling SMP (fifo) block allocation atomically as
part of the ->atomic_check() step.  All those patches should also help
out atomic weston (when those patches eventually land).

* 'msm-next' of git://people.freedesktop.org/~robclark/linux: (36 commits)
  drm/msm: gpu: Add support for the GPMU
  drm/msm: gpu: Add A5XX target support
  drm/msm: Disable interrupts during init
  drm/msm: Remove 'src_clk' from adreno configuration
  drm/msm: gpu: Add OUT_TYPE4 and OUT_TYPE7
  drm/msm: Add adreno_gpu_write64()
  drm/msm: gpu Add new gpu register read/write functions
  drm/msm: gpu: Return error on hw_init failure
  drm/msm: gpu: Cut down the list of "generic" registers to the ones we use
  drm/msm: update generated headers
  drm/msm/adreno: move scratch register dumping to per-gen code
  drm/msm/rd: support for 64b iova
  drm/msm: convert iova to 64b
  drm/msm: set dma_mask properly
  drm/msm: Remove bad calls to of_node_put()
  drm/msm/mdp5: move LM bounds check into plane->atomic_check()
  drm/msm/mdp5: dump smp state on errors too
  drm/msm/mdp5: add debugfs to show smp block status
  drm/msm/mdp5: handle SMP block allocations "atomically"
  drm/msm/mdp5: dynamically assign hw pipes to planes
  ...
parents a90f5831 2401a008

drivers/gpu/drm/msm/Makefile

+4 −0
Original line number Diff line number Diff line
@@ -6,6 +6,8 @@ msm-y := \ 
	adreno/adreno_gpu.o \

	adreno/a3xx_gpu.o \

	adreno/a4xx_gpu.o \

	adreno/a5xx_gpu.o \

	adreno/a5xx_power.o \

	hdmi/hdmi.o \

	hdmi/hdmi_audio.o \

	hdmi/hdmi_bridge.o \
@@ -37,6 +39,7 @@ msm-y := \ 
	mdp/mdp5/mdp5_irq.o \

	mdp/mdp5/mdp5_mdss.o \

	mdp/mdp5/mdp5_kms.o \

	mdp/mdp5/mdp5_pipe.o \

	mdp/mdp5/mdp5_plane.o \

	mdp/mdp5/mdp5_smp.o \

	msm_atomic.o \
@@ -48,6 +51,7 @@ msm-y := \ 
	msm_gem_prime.o \

	msm_gem_shrinker.o \

	msm_gem_submit.o \

	msm_gem_vma.o \

	msm_gpu.o \

	msm_iommu.o \

	msm_perf.o \

drivers/gpu/drm/msm/adreno/a2xx.xml.h

+14 −13
Original line number Diff line number Diff line
@@ -8,16 +8,17 @@ This file was generated by the rules-ng-ng headergen tool in this git repository 
git clone https://github.com/freedreno/envytools.git



The rules-ng-ng source files this header was generated from are:

- /home/robclark/src/freedreno/envytools/rnndb/adreno.xml               (    398 bytes, from 2015-09-24 17:25:31)

- /home/robclark/src/freedreno/envytools/rnndb/adreno.xml               (    431 bytes, from 2016-04-26 17:56:44)

- /home/robclark/src/freedreno/envytools/rnndb/freedreno_copyright.xml  (   1572 bytes, from 2016-02-10 17:07:21)

- /home/robclark/src/freedreno/envytools/rnndb/adreno/a2xx.xml          (  32901 bytes, from 2015-05-20 20:03:14)

- /home/robclark/src/freedreno/envytools/rnndb/adreno/adreno_common.xml (  11518 bytes, from 2016-02-10 21:03:25)

- /home/robclark/src/freedreno/envytools/rnndb/adreno/adreno_pm4.xml    (  16166 bytes, from 2016-02-11 21:20:31)

- /home/robclark/src/freedreno/envytools/rnndb/adreno/a3xx.xml          (  83967 bytes, from 2016-02-10 17:07:21)

- /home/robclark/src/freedreno/envytools/rnndb/adreno/a4xx.xml          ( 109916 bytes, from 2016-02-20 18:44:48)

- /home/robclark/src/freedreno/envytools/rnndb/adreno/a2xx.xml          (  32907 bytes, from 2016-11-26 23:01:08)

- /home/robclark/src/freedreno/envytools/rnndb/adreno/adreno_common.xml (  12025 bytes, from 2016-11-26 23:01:08)

- /home/robclark/src/freedreno/envytools/rnndb/adreno/adreno_pm4.xml    (  22544 bytes, from 2016-11-26 23:01:08)

- /home/robclark/src/freedreno/envytools/rnndb/adreno/a3xx.xml          (  83840 bytes, from 2016-11-26 23:01:08)

- /home/robclark/src/freedreno/envytools/rnndb/adreno/a4xx.xml          ( 110765 bytes, from 2016-11-26 23:01:48)

- /home/robclark/src/freedreno/envytools/rnndb/adreno/a5xx.xml          (  90321 bytes, from 2016-11-28 16:50:05)

- /home/robclark/src/freedreno/envytools/rnndb/adreno/ocmem.xml         (   1773 bytes, from 2015-09-24 17:30:00)



Copyright (C) 2013-2015 by the following authors:

Copyright (C) 2013-2016 by the following authors:

- Rob Clark <robdclark@gmail.com> (robclark)

- Ilia Mirkin <imirkin@alum.mit.edu> (imirkin)
@@ -206,12 +207,12 @@ enum a2xx_rb_copy_sample_select { 
};



enum a2xx_rb_blend_opcode {

	BLEND_DST_PLUS_SRC = 0,

	BLEND_SRC_MINUS_DST = 1,

	BLEND_MIN_DST_SRC = 2,

	BLEND_MAX_DST_SRC = 3,

	BLEND_DST_MINUS_SRC = 4,

	BLEND_DST_PLUS_SRC_BIAS = 5,

	BLEND2_DST_PLUS_SRC = 0,

	BLEND2_SRC_MINUS_DST = 1,

	BLEND2_MIN_DST_SRC = 2,

	BLEND2_MAX_DST_SRC = 3,

	BLEND2_DST_MINUS_SRC = 4,

	BLEND2_DST_PLUS_SRC_BIAS = 5,

};



enum adreno_mmu_clnt_beh {

drivers/gpu/drm/msm/adreno/a3xx.xml.h

+18 −20
Original line number Diff line number Diff line
@@ -8,13 +8,14 @@ This file was generated by the rules-ng-ng headergen tool in this git repository 
git clone https://github.com/freedreno/envytools.git



The rules-ng-ng source files this header was generated from are:

- /home/robclark/src/freedreno/envytools/rnndb/adreno.xml               (    398 bytes, from 2015-09-24 17:25:31)

- /home/robclark/src/freedreno/envytools/rnndb/adreno.xml               (    431 bytes, from 2016-04-26 17:56:44)

- /home/robclark/src/freedreno/envytools/rnndb/freedreno_copyright.xml  (   1572 bytes, from 2016-02-10 17:07:21)

- /home/robclark/src/freedreno/envytools/rnndb/adreno/a2xx.xml          (  32901 bytes, from 2015-05-20 20:03:14)

- /home/robclark/src/freedreno/envytools/rnndb/adreno/adreno_common.xml (  11518 bytes, from 2016-02-10 21:03:25)

- /home/robclark/src/freedreno/envytools/rnndb/adreno/adreno_pm4.xml    (  16166 bytes, from 2016-02-11 21:20:31)

- /home/robclark/src/freedreno/envytools/rnndb/adreno/a3xx.xml          (  83967 bytes, from 2016-02-10 17:07:21)

- /home/robclark/src/freedreno/envytools/rnndb/adreno/a4xx.xml          ( 109916 bytes, from 2016-02-20 18:44:48)

- /home/robclark/src/freedreno/envytools/rnndb/adreno/a2xx.xml          (  32907 bytes, from 2016-11-26 23:01:08)

- /home/robclark/src/freedreno/envytools/rnndb/adreno/adreno_common.xml (  12025 bytes, from 2016-11-26 23:01:08)

- /home/robclark/src/freedreno/envytools/rnndb/adreno/adreno_pm4.xml    (  22544 bytes, from 2016-11-26 23:01:08)

- /home/robclark/src/freedreno/envytools/rnndb/adreno/a3xx.xml          (  83840 bytes, from 2016-11-26 23:01:08)

- /home/robclark/src/freedreno/envytools/rnndb/adreno/a4xx.xml          ( 110765 bytes, from 2016-11-26 23:01:48)

- /home/robclark/src/freedreno/envytools/rnndb/adreno/a5xx.xml          (  90321 bytes, from 2016-11-28 16:50:05)

- /home/robclark/src/freedreno/envytools/rnndb/adreno/ocmem.xml         (   1773 bytes, from 2015-09-24 17:30:00)



Copyright (C) 2013-2016 by the following authors:
@@ -129,10 +130,14 @@ enum a3xx_tex_fmt { 
	TFMT_Z16_UNORM = 9,

	TFMT_X8Z24_UNORM = 10,

	TFMT_Z32_FLOAT = 11,

	TFMT_NV12_UV_TILED = 17,

	TFMT_NV12_Y_TILED = 19,

	TFMT_NV12_UV = 21,

	TFMT_NV12_Y = 23,

	TFMT_UV_64X32 = 16,

	TFMT_VU_64X32 = 17,

	TFMT_Y_64X32 = 18,

	TFMT_NV12_64X32 = 19,

	TFMT_UV_LINEAR = 20,

	TFMT_VU_LINEAR = 21,

	TFMT_Y_LINEAR = 22,

	TFMT_NV12_LINEAR = 23,

	TFMT_I420_Y = 24,

	TFMT_I420_U = 26,

	TFMT_I420_V = 27,
@@ -525,14 +530,6 @@ enum a3xx_uche_perfcounter_select { 
	UCHE_UCHEPERF_ACTIVE_CYCLES = 20,

};



enum a3xx_rb_blend_opcode {

	BLEND_DST_PLUS_SRC = 0,

	BLEND_SRC_MINUS_DST = 1,

	BLEND_DST_MINUS_SRC = 2,

	BLEND_MIN_DST_SRC = 3,

	BLEND_MAX_DST_SRC = 4,

};



enum a3xx_intp_mode {

	SMOOTH = 0,

	FLAT = 1,
@@ -1393,13 +1390,14 @@ static inline uint32_t A3XX_RB_COPY_CONTROL_MODE(enum adreno_rb_copy_control_mod 
{

	return ((val) << A3XX_RB_COPY_CONTROL_MODE__SHIFT) & A3XX_RB_COPY_CONTROL_MODE__MASK;

}

#define A3XX_RB_COPY_CONTROL_MSAA_SRGB_DOWNSAMPLE		0x00000080

#define A3XX_RB_COPY_CONTROL_FASTCLEAR__MASK			0x00000f00

#define A3XX_RB_COPY_CONTROL_FASTCLEAR__SHIFT			8

static inline uint32_t A3XX_RB_COPY_CONTROL_FASTCLEAR(uint32_t val)

{

	return ((val) << A3XX_RB_COPY_CONTROL_FASTCLEAR__SHIFT) & A3XX_RB_COPY_CONTROL_FASTCLEAR__MASK;

}

#define A3XX_RB_COPY_CONTROL_UNK12				0x00001000

#define A3XX_RB_COPY_CONTROL_DEPTH32_RESOLVE			0x00001000

#define A3XX_RB_COPY_CONTROL_GMEM_BASE__MASK			0xffffc000

#define A3XX_RB_COPY_CONTROL_GMEM_BASE__SHIFT			14

static inline uint32_t A3XX_RB_COPY_CONTROL_GMEM_BASE(uint32_t val)
@@ -1472,7 +1470,7 @@ static inline uint32_t A3XX_RB_DEPTH_CONTROL_ZFUNC(enum adreno_compare_func val) 
{

	return ((val) << A3XX_RB_DEPTH_CONTROL_ZFUNC__SHIFT) & A3XX_RB_DEPTH_CONTROL_ZFUNC__MASK;

}

#define A3XX_RB_DEPTH_CONTROL_BF_ENABLE				0x00000080

#define A3XX_RB_DEPTH_CONTROL_Z_CLAMP_ENABLE			0x00000080

#define A3XX_RB_DEPTH_CONTROL_Z_TEST_ENABLE			0x80000000



#define REG_A3XX_RB_DEPTH_CLEAR					0x00002101

drivers/gpu/drm/msm/adreno/a3xx_gpu.c

+22 −90
Original line number Diff line number Diff line
@@ -41,7 +41,7 @@ extern bool hang_debug; 


static void a3xx_dump(struct msm_gpu *gpu);



static void a3xx_me_init(struct msm_gpu *gpu)

static bool a3xx_me_init(struct msm_gpu *gpu)

{

	struct msm_ringbuffer *ring = gpu->rb;
@@ -65,7 +65,7 @@ static void a3xx_me_init(struct msm_gpu *gpu) 
	OUT_RING(ring, 0x00000000);



	gpu->funcs->flush(gpu);

	gpu->funcs->idle(gpu);

	return gpu->funcs->idle(gpu);

}



static int a3xx_hw_init(struct msm_gpu *gpu)
@@ -294,15 +294,20 @@ static int a3xx_hw_init(struct msm_gpu *gpu) 
	/* clear ME_HALT to start micro engine */

	gpu_write(gpu, REG_AXXX_CP_ME_CNTL, 0);



	a3xx_me_init(gpu);



	return 0;

	return a3xx_me_init(gpu) ? 0 : -EINVAL;

}



static void a3xx_recover(struct msm_gpu *gpu)

{

	int i;



	adreno_dump_info(gpu);



	for (i = 0; i < 8; i++) {

		printk("CP_SCRATCH_REG%d: %u\n", i,

			gpu_read(gpu, REG_AXXX_CP_SCRATCH_REG0 + i));

	}



	/* dump registers before resetting gpu, if enabled: */

	if (hang_debug)

		a3xx_dump(gpu);
@@ -330,17 +335,22 @@ static void a3xx_destroy(struct msm_gpu *gpu) 
	kfree(a3xx_gpu);

}



static void a3xx_idle(struct msm_gpu *gpu)

static bool a3xx_idle(struct msm_gpu *gpu)

{

	/* wait for ringbuffer to drain: */

	adreno_idle(gpu);

	if (!adreno_idle(gpu))

		return false;



	/* then wait for GPU to finish: */

	if (spin_until(!(gpu_read(gpu, REG_A3XX_RBBM_STATUS) &

			A3XX_RBBM_STATUS_GPU_BUSY)))

			A3XX_RBBM_STATUS_GPU_BUSY))) {

		DRM_ERROR("%s: timeout waiting for GPU to idle!\n", gpu->name);



		/* TODO maybe we need to reset GPU here to recover from hang? */

		return false;

	}



	return true;

}



static irqreturn_t a3xx_irq(struct msm_gpu *gpu)
@@ -419,91 +429,13 @@ static void a3xx_dump(struct msm_gpu *gpu) 
}

/* Register offset defines for A3XX */

static const unsigned int a3xx_register_offsets[REG_ADRENO_REGISTER_MAX] = {

	REG_ADRENO_DEFINE(REG_ADRENO_CP_DEBUG, REG_AXXX_CP_DEBUG),

	REG_ADRENO_DEFINE(REG_ADRENO_CP_ME_RAM_WADDR, REG_AXXX_CP_ME_RAM_WADDR),

	REG_ADRENO_DEFINE(REG_ADRENO_CP_ME_RAM_DATA, REG_AXXX_CP_ME_RAM_DATA),

	REG_ADRENO_DEFINE(REG_ADRENO_CP_PFP_UCODE_DATA,

			REG_A3XX_CP_PFP_UCODE_DATA),

	REG_ADRENO_DEFINE(REG_ADRENO_CP_PFP_UCODE_ADDR,

			REG_A3XX_CP_PFP_UCODE_ADDR),

	REG_ADRENO_DEFINE(REG_ADRENO_CP_WFI_PEND_CTR, REG_A3XX_CP_WFI_PEND_CTR),

	REG_ADRENO_DEFINE(REG_ADRENO_CP_RB_BASE, REG_AXXX_CP_RB_BASE),

	REG_ADRENO_SKIP(REG_ADRENO_CP_RB_BASE_HI),

	REG_ADRENO_DEFINE(REG_ADRENO_CP_RB_RPTR_ADDR, REG_AXXX_CP_RB_RPTR_ADDR),

	REG_ADRENO_SKIP(REG_ADRENO_CP_RB_RPTR_ADDR_HI),

	REG_ADRENO_DEFINE(REG_ADRENO_CP_RB_RPTR, REG_AXXX_CP_RB_RPTR),

	REG_ADRENO_DEFINE(REG_ADRENO_CP_RB_WPTR, REG_AXXX_CP_RB_WPTR),

	REG_ADRENO_DEFINE(REG_ADRENO_CP_PROTECT_CTRL, REG_A3XX_CP_PROTECT_CTRL),

	REG_ADRENO_DEFINE(REG_ADRENO_CP_ME_CNTL, REG_AXXX_CP_ME_CNTL),

	REG_ADRENO_DEFINE(REG_ADRENO_CP_RB_CNTL, REG_AXXX_CP_RB_CNTL),

	REG_ADRENO_DEFINE(REG_ADRENO_CP_IB1_BASE, REG_AXXX_CP_IB1_BASE),

	REG_ADRENO_DEFINE(REG_ADRENO_CP_IB1_BUFSZ, REG_AXXX_CP_IB1_BUFSZ),

	REG_ADRENO_DEFINE(REG_ADRENO_CP_IB2_BASE, REG_AXXX_CP_IB2_BASE),

	REG_ADRENO_DEFINE(REG_ADRENO_CP_IB2_BUFSZ, REG_AXXX_CP_IB2_BUFSZ),

	REG_ADRENO_DEFINE(REG_ADRENO_CP_TIMESTAMP, REG_AXXX_CP_SCRATCH_REG0),

	REG_ADRENO_DEFINE(REG_ADRENO_CP_ME_RAM_RADDR, REG_AXXX_CP_ME_RAM_RADDR),

	REG_ADRENO_DEFINE(REG_ADRENO_SCRATCH_ADDR, REG_AXXX_SCRATCH_ADDR),

	REG_ADRENO_DEFINE(REG_ADRENO_SCRATCH_UMSK, REG_AXXX_SCRATCH_UMSK),

	REG_ADRENO_DEFINE(REG_ADRENO_CP_ROQ_ADDR, REG_A3XX_CP_ROQ_ADDR),

	REG_ADRENO_DEFINE(REG_ADRENO_CP_ROQ_DATA, REG_A3XX_CP_ROQ_DATA),

	REG_ADRENO_DEFINE(REG_ADRENO_CP_MERCIU_ADDR, REG_A3XX_CP_MERCIU_ADDR),

	REG_ADRENO_DEFINE(REG_ADRENO_CP_MERCIU_DATA, REG_A3XX_CP_MERCIU_DATA),

	REG_ADRENO_DEFINE(REG_ADRENO_CP_MERCIU_DATA2, REG_A3XX_CP_MERCIU_DATA2),

	REG_ADRENO_DEFINE(REG_ADRENO_CP_MEQ_ADDR, REG_A3XX_CP_MEQ_ADDR),

	REG_ADRENO_DEFINE(REG_ADRENO_CP_MEQ_DATA, REG_A3XX_CP_MEQ_DATA),

	REG_ADRENO_DEFINE(REG_ADRENO_CP_HW_FAULT, REG_A3XX_CP_HW_FAULT),

	REG_ADRENO_DEFINE(REG_ADRENO_CP_PROTECT_STATUS,

			REG_A3XX_CP_PROTECT_STATUS),

	REG_ADRENO_DEFINE(REG_ADRENO_RBBM_STATUS, REG_A3XX_RBBM_STATUS),

	REG_ADRENO_DEFINE(REG_ADRENO_RBBM_PERFCTR_CTL,

			REG_A3XX_RBBM_PERFCTR_CTL),

	REG_ADRENO_DEFINE(REG_ADRENO_RBBM_PERFCTR_LOAD_CMD0,

			REG_A3XX_RBBM_PERFCTR_LOAD_CMD0),

	REG_ADRENO_DEFINE(REG_ADRENO_RBBM_PERFCTR_LOAD_CMD1,

			REG_A3XX_RBBM_PERFCTR_LOAD_CMD1),

	REG_ADRENO_DEFINE(REG_ADRENO_RBBM_PERFCTR_PWR_1_LO,

			REG_A3XX_RBBM_PERFCTR_PWR_1_LO),

	REG_ADRENO_DEFINE(REG_ADRENO_RBBM_INT_0_MASK, REG_A3XX_RBBM_INT_0_MASK),

	REG_ADRENO_DEFINE(REG_ADRENO_RBBM_INT_0_STATUS,

			REG_A3XX_RBBM_INT_0_STATUS),

	REG_ADRENO_DEFINE(REG_ADRENO_RBBM_AHB_ERROR_STATUS,

			REG_A3XX_RBBM_AHB_ERROR_STATUS),

	REG_ADRENO_DEFINE(REG_ADRENO_RBBM_AHB_CMD, REG_A3XX_RBBM_AHB_CMD),

	REG_ADRENO_DEFINE(REG_ADRENO_RBBM_INT_CLEAR_CMD,

			REG_A3XX_RBBM_INT_CLEAR_CMD),

	REG_ADRENO_DEFINE(REG_ADRENO_RBBM_CLOCK_CTL, REG_A3XX_RBBM_CLOCK_CTL),

	REG_ADRENO_DEFINE(REG_ADRENO_VPC_DEBUG_RAM_SEL,

			REG_A3XX_VPC_VPC_DEBUG_RAM_SEL),

	REG_ADRENO_DEFINE(REG_ADRENO_VPC_DEBUG_RAM_READ,

			REG_A3XX_VPC_VPC_DEBUG_RAM_READ),

	REG_ADRENO_DEFINE(REG_ADRENO_VSC_SIZE_ADDRESS,

			REG_A3XX_VSC_SIZE_ADDRESS),

	REG_ADRENO_DEFINE(REG_ADRENO_VFD_CONTROL_0, REG_A3XX_VFD_CONTROL_0),

	REG_ADRENO_DEFINE(REG_ADRENO_VFD_INDEX_MAX, REG_A3XX_VFD_INDEX_MAX),

	REG_ADRENO_DEFINE(REG_ADRENO_SP_VS_PVT_MEM_ADDR_REG,

			REG_A3XX_SP_VS_PVT_MEM_ADDR_REG),

	REG_ADRENO_DEFINE(REG_ADRENO_SP_FS_PVT_MEM_ADDR_REG,

			REG_A3XX_SP_FS_PVT_MEM_ADDR_REG),

	REG_ADRENO_DEFINE(REG_ADRENO_SP_VS_OBJ_START_REG,

			REG_A3XX_SP_VS_OBJ_START_REG),

	REG_ADRENO_DEFINE(REG_ADRENO_SP_FS_OBJ_START_REG,

			REG_A3XX_SP_FS_OBJ_START_REG),

	REG_ADRENO_DEFINE(REG_ADRENO_PA_SC_AA_CONFIG, REG_A3XX_PA_SC_AA_CONFIG),

	REG_ADRENO_DEFINE(REG_ADRENO_RBBM_PM_OVERRIDE2,

			REG_A3XX_RBBM_PM_OVERRIDE2),

	REG_ADRENO_DEFINE(REG_ADRENO_SCRATCH_REG2, REG_AXXX_CP_SCRATCH_REG2),

	REG_ADRENO_DEFINE(REG_ADRENO_SQ_GPR_MANAGEMENT,

			REG_A3XX_SQ_GPR_MANAGEMENT),

	REG_ADRENO_DEFINE(REG_ADRENO_SQ_INST_STORE_MANAGMENT,

			REG_A3XX_SQ_INST_STORE_MANAGMENT),

	REG_ADRENO_DEFINE(REG_ADRENO_TP0_CHICKEN, REG_A3XX_TP0_CHICKEN),

	REG_ADRENO_DEFINE(REG_ADRENO_RBBM_RBBM_CTL, REG_A3XX_RBBM_RBBM_CTL),

	REG_ADRENO_DEFINE(REG_ADRENO_RBBM_SW_RESET_CMD,

			REG_A3XX_RBBM_SW_RESET_CMD),

	REG_ADRENO_DEFINE(REG_ADRENO_UCHE_INVALIDATE0,

			REG_A3XX_UCHE_CACHE_INVALIDATE0_REG),

	REG_ADRENO_DEFINE(REG_ADRENO_RBBM_PERFCTR_LOAD_VALUE_LO,

			REG_A3XX_RBBM_PERFCTR_LOAD_VALUE_LO),

	REG_ADRENO_DEFINE(REG_ADRENO_RBBM_PERFCTR_LOAD_VALUE_HI,

			REG_A3XX_RBBM_PERFCTR_LOAD_VALUE_HI),

};



static const struct adreno_gpu_funcs funcs = {
@@ -583,7 +515,7 @@ struct msm_gpu *a3xx_gpu_init(struct drm_device *dev) 
#endif

	}



	if (!gpu->mmu) {

	if (!gpu->aspace) {

		/* TODO we think it is possible to configure the GPU to

		 * restrict access to VRAM carveout.  But the required

		 * registers are unknown.  For now just bail out and

drivers/gpu/drm/msm/adreno/a4xx.xml.h

+80 −31
Original line number Diff line number Diff line
@@ -8,13 +8,14 @@ This file was generated by the rules-ng-ng headergen tool in this git repository 
git clone https://github.com/freedreno/envytools.git



The rules-ng-ng source files this header was generated from are:

- /home/robclark/src/freedreno/envytools/rnndb/adreno.xml               (    398 bytes, from 2015-09-24 17:25:31)

- /home/robclark/src/freedreno/envytools/rnndb/adreno.xml               (    431 bytes, from 2016-04-26 17:56:44)

- /home/robclark/src/freedreno/envytools/rnndb/freedreno_copyright.xml  (   1572 bytes, from 2016-02-10 17:07:21)

- /home/robclark/src/freedreno/envytools/rnndb/adreno/a2xx.xml          (  32901 bytes, from 2015-05-20 20:03:14)

- /home/robclark/src/freedreno/envytools/rnndb/adreno/adreno_common.xml (  11518 bytes, from 2016-02-10 21:03:25)

- /home/robclark/src/freedreno/envytools/rnndb/adreno/adreno_pm4.xml    (  16166 bytes, from 2016-02-11 21:20:31)

- /home/robclark/src/freedreno/envytools/rnndb/adreno/a3xx.xml          (  83967 bytes, from 2016-02-10 17:07:21)

- /home/robclark/src/freedreno/envytools/rnndb/adreno/a4xx.xml          ( 109916 bytes, from 2016-02-20 18:44:48)

- /home/robclark/src/freedreno/envytools/rnndb/adreno/a2xx.xml          (  32907 bytes, from 2016-11-26 23:01:08)

- /home/robclark/src/freedreno/envytools/rnndb/adreno/adreno_common.xml (  12025 bytes, from 2016-11-26 23:01:08)

- /home/robclark/src/freedreno/envytools/rnndb/adreno/adreno_pm4.xml    (  22544 bytes, from 2016-11-26 23:01:08)

- /home/robclark/src/freedreno/envytools/rnndb/adreno/a3xx.xml          (  83840 bytes, from 2016-11-26 23:01:08)

- /home/robclark/src/freedreno/envytools/rnndb/adreno/a4xx.xml          ( 110765 bytes, from 2016-11-26 23:01:48)

- /home/robclark/src/freedreno/envytools/rnndb/adreno/a5xx.xml          (  90321 bytes, from 2016-11-28 16:50:05)

- /home/robclark/src/freedreno/envytools/rnndb/adreno/ocmem.xml         (   1773 bytes, from 2015-09-24 17:30:00)



Copyright (C) 2013-2016 by the following authors:
@@ -46,6 +47,9 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. 
enum a4xx_color_fmt {

	RB4_A8_UNORM = 1,

	RB4_R8_UNORM = 2,

	RB4_R8_SNORM = 3,

	RB4_R8_UINT = 4,

	RB4_R8_SINT = 5,

	RB4_R4G4B4A4_UNORM = 8,

	RB4_R5G5B5A1_UNORM = 10,

	RB4_R5G6B5_UNORM = 14,
@@ -89,17 +93,10 @@ enum a4xx_color_fmt { 


enum a4xx_tile_mode {

	TILE4_LINEAR = 0,

	TILE4_2 = 2,

	TILE4_3 = 3,

};



enum a4xx_rb_blend_opcode {

	BLEND_DST_PLUS_SRC = 0,

	BLEND_SRC_MINUS_DST = 1,

	BLEND_DST_MINUS_SRC = 2,

	BLEND_MIN_DST_SRC = 3,

	BLEND_MAX_DST_SRC = 4,

};



enum a4xx_vtx_fmt {

	VFMT4_32_FLOAT = 1,

	VFMT4_32_32_FLOAT = 2,
@@ -940,6 +937,7 @@ static inline uint32_t A4XX_RB_MODE_CONTROL_HEIGHT(uint32_t val) 
{

	return ((val >> 5) << A4XX_RB_MODE_CONTROL_HEIGHT__SHIFT) & A4XX_RB_MODE_CONTROL_HEIGHT__MASK;

}

#define A4XX_RB_MODE_CONTROL_ENABLE_GMEM			0x00010000



#define REG_A4XX_RB_RENDER_CONTROL				0x000020a1

#define A4XX_RB_RENDER_CONTROL_BINNING_PASS			0x00000001
@@ -1043,7 +1041,7 @@ static inline uint32_t A4XX_RB_MRT_BLEND_CONTROL_RGB_SRC_FACTOR(enum adreno_rb_b 
}

#define A4XX_RB_MRT_BLEND_CONTROL_RGB_BLEND_OPCODE__MASK	0x000000e0

#define A4XX_RB_MRT_BLEND_CONTROL_RGB_BLEND_OPCODE__SHIFT	5

static inline uint32_t A4XX_RB_MRT_BLEND_CONTROL_RGB_BLEND_OPCODE(enum a4xx_rb_blend_opcode val)

static inline uint32_t A4XX_RB_MRT_BLEND_CONTROL_RGB_BLEND_OPCODE(enum a3xx_rb_blend_opcode val)

{

	return ((val) << A4XX_RB_MRT_BLEND_CONTROL_RGB_BLEND_OPCODE__SHIFT) & A4XX_RB_MRT_BLEND_CONTROL_RGB_BLEND_OPCODE__MASK;

}
@@ -1061,7 +1059,7 @@ static inline uint32_t A4XX_RB_MRT_BLEND_CONTROL_ALPHA_SRC_FACTOR(enum adreno_rb 
}

#define A4XX_RB_MRT_BLEND_CONTROL_ALPHA_BLEND_OPCODE__MASK	0x00e00000

#define A4XX_RB_MRT_BLEND_CONTROL_ALPHA_BLEND_OPCODE__SHIFT	21

static inline uint32_t A4XX_RB_MRT_BLEND_CONTROL_ALPHA_BLEND_OPCODE(enum a4xx_rb_blend_opcode val)

static inline uint32_t A4XX_RB_MRT_BLEND_CONTROL_ALPHA_BLEND_OPCODE(enum a3xx_rb_blend_opcode val)

{

	return ((val) << A4XX_RB_MRT_BLEND_CONTROL_ALPHA_BLEND_OPCODE__SHIFT) & A4XX_RB_MRT_BLEND_CONTROL_ALPHA_BLEND_OPCODE__MASK;

}
@@ -1073,12 +1071,18 @@ static inline uint32_t A4XX_RB_MRT_BLEND_CONTROL_ALPHA_DEST_FACTOR(enum adreno_r 
}



#define REG_A4XX_RB_BLEND_RED					0x000020f0

#define A4XX_RB_BLEND_RED_UINT__MASK				0x0000ffff

#define A4XX_RB_BLEND_RED_UINT__MASK				0x000000ff

#define A4XX_RB_BLEND_RED_UINT__SHIFT				0

static inline uint32_t A4XX_RB_BLEND_RED_UINT(uint32_t val)

{

	return ((val) << A4XX_RB_BLEND_RED_UINT__SHIFT) & A4XX_RB_BLEND_RED_UINT__MASK;

}

#define A4XX_RB_BLEND_RED_SINT__MASK				0x0000ff00

#define A4XX_RB_BLEND_RED_SINT__SHIFT				8

static inline uint32_t A4XX_RB_BLEND_RED_SINT(uint32_t val)

{

	return ((val) << A4XX_RB_BLEND_RED_SINT__SHIFT) & A4XX_RB_BLEND_RED_SINT__MASK;

}

#define A4XX_RB_BLEND_RED_FLOAT__MASK				0xffff0000

#define A4XX_RB_BLEND_RED_FLOAT__SHIFT				16

static inline uint32_t A4XX_RB_BLEND_RED_FLOAT(float val)
@@ -1095,12 +1099,18 @@ static inline uint32_t A4XX_RB_BLEND_RED_F32(float val) 
}



#define REG_A4XX_RB_BLEND_GREEN					0x000020f2

#define A4XX_RB_BLEND_GREEN_UINT__MASK				0x0000ffff

#define A4XX_RB_BLEND_GREEN_UINT__MASK				0x000000ff

#define A4XX_RB_BLEND_GREEN_UINT__SHIFT				0

static inline uint32_t A4XX_RB_BLEND_GREEN_UINT(uint32_t val)

{

	return ((val) << A4XX_RB_BLEND_GREEN_UINT__SHIFT) & A4XX_RB_BLEND_GREEN_UINT__MASK;

}

#define A4XX_RB_BLEND_GREEN_SINT__MASK				0x0000ff00

#define A4XX_RB_BLEND_GREEN_SINT__SHIFT				8

static inline uint32_t A4XX_RB_BLEND_GREEN_SINT(uint32_t val)

{

	return ((val) << A4XX_RB_BLEND_GREEN_SINT__SHIFT) & A4XX_RB_BLEND_GREEN_SINT__MASK;

}

#define A4XX_RB_BLEND_GREEN_FLOAT__MASK				0xffff0000

#define A4XX_RB_BLEND_GREEN_FLOAT__SHIFT			16

static inline uint32_t A4XX_RB_BLEND_GREEN_FLOAT(float val)
@@ -1117,12 +1127,18 @@ static inline uint32_t A4XX_RB_BLEND_GREEN_F32(float val) 
}



#define REG_A4XX_RB_BLEND_BLUE					0x000020f4

#define A4XX_RB_BLEND_BLUE_UINT__MASK				0x0000ffff

#define A4XX_RB_BLEND_BLUE_UINT__MASK				0x000000ff

#define A4XX_RB_BLEND_BLUE_UINT__SHIFT				0

static inline uint32_t A4XX_RB_BLEND_BLUE_UINT(uint32_t val)

{

	return ((val) << A4XX_RB_BLEND_BLUE_UINT__SHIFT) & A4XX_RB_BLEND_BLUE_UINT__MASK;

}

#define A4XX_RB_BLEND_BLUE_SINT__MASK				0x0000ff00

#define A4XX_RB_BLEND_BLUE_SINT__SHIFT				8

static inline uint32_t A4XX_RB_BLEND_BLUE_SINT(uint32_t val)

{

	return ((val) << A4XX_RB_BLEND_BLUE_SINT__SHIFT) & A4XX_RB_BLEND_BLUE_SINT__MASK;

}

#define A4XX_RB_BLEND_BLUE_FLOAT__MASK				0xffff0000

#define A4XX_RB_BLEND_BLUE_FLOAT__SHIFT				16

static inline uint32_t A4XX_RB_BLEND_BLUE_FLOAT(float val)
@@ -1139,12 +1155,18 @@ static inline uint32_t A4XX_RB_BLEND_BLUE_F32(float val) 
}



#define REG_A4XX_RB_BLEND_ALPHA					0x000020f6

#define A4XX_RB_BLEND_ALPHA_UINT__MASK				0x0000ffff

#define A4XX_RB_BLEND_ALPHA_UINT__MASK				0x000000ff

#define A4XX_RB_BLEND_ALPHA_UINT__SHIFT				0

static inline uint32_t A4XX_RB_BLEND_ALPHA_UINT(uint32_t val)

{

	return ((val) << A4XX_RB_BLEND_ALPHA_UINT__SHIFT) & A4XX_RB_BLEND_ALPHA_UINT__MASK;

}

#define A4XX_RB_BLEND_ALPHA_SINT__MASK				0x0000ff00

#define A4XX_RB_BLEND_ALPHA_SINT__SHIFT				8

static inline uint32_t A4XX_RB_BLEND_ALPHA_SINT(uint32_t val)

{

	return ((val) << A4XX_RB_BLEND_ALPHA_SINT__SHIFT) & A4XX_RB_BLEND_ALPHA_SINT__MASK;

}

#define A4XX_RB_BLEND_ALPHA_FLOAT__MASK				0xffff0000

#define A4XX_RB_BLEND_ALPHA_FLOAT__SHIFT			16

static inline uint32_t A4XX_RB_BLEND_ALPHA_FLOAT(float val)
@@ -1348,7 +1370,7 @@ static inline uint32_t A4XX_RB_DEPTH_CONTROL_ZFUNC(enum adreno_compare_func val) 
{

	return ((val) << A4XX_RB_DEPTH_CONTROL_ZFUNC__SHIFT) & A4XX_RB_DEPTH_CONTROL_ZFUNC__MASK;

}

#define A4XX_RB_DEPTH_CONTROL_BF_ENABLE				0x00000080

#define A4XX_RB_DEPTH_CONTROL_Z_CLAMP_ENABLE			0x00000080

#define A4XX_RB_DEPTH_CONTROL_EARLY_Z_DISABLE			0x00010000

#define A4XX_RB_DEPTH_CONTROL_FORCE_FRAGZ_TO_FS			0x00020000

#define A4XX_RB_DEPTH_CONTROL_Z_TEST_ENABLE			0x80000000
@@ -2177,11 +2199,23 @@ static inline uint32_t REG_A4XX_RBBM_CLOCK_DELAY_RB_MARB_CCU_L1_REG(uint32_t i0) 


#define REG_A4XX_CP_DRAW_STATE_ADDR				0x00000232



#define REG_A4XX_CP_PROTECT_REG_0				0x00000240



static inline uint32_t REG_A4XX_CP_PROTECT(uint32_t i0) { return 0x00000240 + 0x1*i0; }



static inline uint32_t REG_A4XX_CP_PROTECT_REG(uint32_t i0) { return 0x00000240 + 0x1*i0; }

#define A4XX_CP_PROTECT_REG_BASE_ADDR__MASK			0x0001ffff

#define A4XX_CP_PROTECT_REG_BASE_ADDR__SHIFT			0

static inline uint32_t A4XX_CP_PROTECT_REG_BASE_ADDR(uint32_t val)

{

	return ((val) << A4XX_CP_PROTECT_REG_BASE_ADDR__SHIFT) & A4XX_CP_PROTECT_REG_BASE_ADDR__MASK;

}

#define A4XX_CP_PROTECT_REG_MASK_LEN__MASK			0x1f000000

#define A4XX_CP_PROTECT_REG_MASK_LEN__SHIFT			24

static inline uint32_t A4XX_CP_PROTECT_REG_MASK_LEN(uint32_t val)

{

	return ((val) << A4XX_CP_PROTECT_REG_MASK_LEN__SHIFT) & A4XX_CP_PROTECT_REG_MASK_LEN__MASK;

}

#define A4XX_CP_PROTECT_REG_TRAP_WRITE				0x20000000

#define A4XX_CP_PROTECT_REG_TRAP_READ				0x40000000



#define REG_A4XX_CP_PROTECT_CTRL				0x00000250
@@ -2272,7 +2306,7 @@ static inline uint32_t A4XX_SP_VS_CTRL_REG0_HALFREGFOOTPRINT(uint32_t val) 
{

	return ((val) << A4XX_SP_VS_CTRL_REG0_HALFREGFOOTPRINT__SHIFT) & A4XX_SP_VS_CTRL_REG0_HALFREGFOOTPRINT__MASK;

}

#define A4XX_SP_VS_CTRL_REG0_FULLREGFOOTPRINT__MASK		0x0003fc00

#define A4XX_SP_VS_CTRL_REG0_FULLREGFOOTPRINT__MASK		0x0000fc00

#define A4XX_SP_VS_CTRL_REG0_FULLREGFOOTPRINT__SHIFT		10

static inline uint32_t A4XX_SP_VS_CTRL_REG0_FULLREGFOOTPRINT(uint32_t val)

{
@@ -2420,7 +2454,7 @@ static inline uint32_t A4XX_SP_FS_CTRL_REG0_HALFREGFOOTPRINT(uint32_t val) 
{

	return ((val) << A4XX_SP_FS_CTRL_REG0_HALFREGFOOTPRINT__SHIFT) & A4XX_SP_FS_CTRL_REG0_HALFREGFOOTPRINT__MASK;

}

#define A4XX_SP_FS_CTRL_REG0_FULLREGFOOTPRINT__MASK		0x0003fc00

#define A4XX_SP_FS_CTRL_REG0_FULLREGFOOTPRINT__MASK		0x0000fc00

#define A4XX_SP_FS_CTRL_REG0_FULLREGFOOTPRINT__SHIFT		10

static inline uint32_t A4XX_SP_FS_CTRL_REG0_FULLREGFOOTPRINT(uint32_t val)

{
@@ -3117,6 +3151,8 @@ static inline uint32_t A4XX_TPL1_TP_TEX_COUNT_GS(uint32_t val) 


#define REG_A4XX_GRAS_CL_CLIP_CNTL				0x00002000

#define A4XX_GRAS_CL_CLIP_CNTL_CLIP_DISABLE			0x00008000

#define A4XX_GRAS_CL_CLIP_CNTL_ZNEAR_CLIP_DISABLE		0x00010000

#define A4XX_GRAS_CL_CLIP_CNTL_ZFAR_CLIP_DISABLE		0x00020000

#define A4XX_GRAS_CL_CLIP_CNTL_ZERO_GB_SCALE_Z			0x00400000



#define REG_A4XX_GRAS_CLEAR_CNTL				0x00002003
@@ -3253,6 +3289,7 @@ static inline uint32_t A4XX_GRAS_SU_MODE_CONTROL_LINEHALFWIDTH(float val) 
	return ((((int32_t)(val * 4.0))) << A4XX_GRAS_SU_MODE_CONTROL_LINEHALFWIDTH__SHIFT) & A4XX_GRAS_SU_MODE_CONTROL_LINEHALFWIDTH__MASK;

}

#define A4XX_GRAS_SU_MODE_CONTROL_POLY_OFFSET			0x00000800

#define A4XX_GRAS_SU_MODE_CONTROL_MSAA_ENABLE			0x00002000

#define A4XX_GRAS_SU_MODE_CONTROL_RENDERING_PASS		0x00100000



#define REG_A4XX_GRAS_SC_CONTROL				0x0000207b
@@ -3670,6 +3707,8 @@ static inline uint32_t A4XX_HLSQ_GS_CONTROL_REG_INSTRLENGTH(uint32_t val) 
#define REG_A4XX_PC_BINNING_COMMAND				0x00000d00

#define A4XX_PC_BINNING_COMMAND_BINNING_ENABLE			0x00000001



#define REG_A4XX_PC_TESSFACTOR_ADDR				0x00000d08



#define REG_A4XX_PC_DRAWCALL_SETUP_OVERRIDE			0x00000d0c



#define REG_A4XX_PC_PERFCTR_PC_SEL_0				0x00000d10
@@ -3690,6 +3729,20 @@ static inline uint32_t A4XX_HLSQ_GS_CONTROL_REG_INSTRLENGTH(uint32_t val) 


#define REG_A4XX_PC_BIN_BASE					0x000021c0



#define REG_A4XX_PC_VSTREAM_CONTROL				0x000021c2

#define A4XX_PC_VSTREAM_CONTROL_SIZE__MASK			0x003f0000

#define A4XX_PC_VSTREAM_CONTROL_SIZE__SHIFT			16

static inline uint32_t A4XX_PC_VSTREAM_CONTROL_SIZE(uint32_t val)

{

	return ((val) << A4XX_PC_VSTREAM_CONTROL_SIZE__SHIFT) & A4XX_PC_VSTREAM_CONTROL_SIZE__MASK;

}

#define A4XX_PC_VSTREAM_CONTROL_N__MASK				0x07c00000

#define A4XX_PC_VSTREAM_CONTROL_N__SHIFT			22

static inline uint32_t A4XX_PC_VSTREAM_CONTROL_N(uint32_t val)

{

	return ((val) << A4XX_PC_VSTREAM_CONTROL_N__SHIFT) & A4XX_PC_VSTREAM_CONTROL_N__MASK;

}



#define REG_A4XX_PC_PRIM_VTX_CNTL				0x000021c4

#define A4XX_PC_PRIM_VTX_CNTL_VAROUT__MASK			0x0000000f

#define A4XX_PC_PRIM_VTX_CNTL_VAROUT__SHIFT			0
@@ -3752,12 +3805,8 @@ static inline uint32_t A4XX_PC_HS_PARAM_SPACING(enum a4xx_tess_spacing val) 
{

	return ((val) << A4XX_PC_HS_PARAM_SPACING__SHIFT) & A4XX_PC_HS_PARAM_SPACING__MASK;

}

#define A4XX_PC_HS_PARAM_PRIMTYPE__MASK				0x01800000

#define A4XX_PC_HS_PARAM_PRIMTYPE__SHIFT			23

static inline uint32_t A4XX_PC_HS_PARAM_PRIMTYPE(enum adreno_pa_su_sc_draw val)

{

	return ((val) << A4XX_PC_HS_PARAM_PRIMTYPE__SHIFT) & A4XX_PC_HS_PARAM_PRIMTYPE__MASK;

}

#define A4XX_PC_HS_PARAM_CW					0x00800000

#define A4XX_PC_HS_PARAM_CONNECTED				0x01000000



#define REG_A4XX_VBIF_VERSION					0x00003000