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Commit f4274e23 authored by Dave Airlie's avatar Dave Airlie
Browse files

Merge tag 'drm-intel-fixes-2015-04-08' of git://anongit.freedesktop.org/drm-intel into drm-fixes 

three commits, all cc: stable, to address Baytrail
suspend/resume issues.

* tag 'drm-intel-fixes-2015-04-08' of git://anongit.freedesktop.org/drm-intel:
  drm/i915/vlv: remove wait for previous GFX clk disable request
  drm/i915/chv: Remove Wait for a previous gfx force-off
  drm/i915/vlv: save/restore the power context base reg
parents 04bdf441 5df0582b

drivers/gpu/drm/i915/i915_drv.c

+2 −12
Original line number Diff line number Diff line
@@ -1095,6 +1095,7 @@ static void vlv_save_gunit_s0ix_state(struct drm_i915_private *dev_priv) 
	/* Gunit-Display CZ domain, 0x182028-0x1821CF */

	s->gu_ctl0		= I915_READ(VLV_GU_CTL0);

	s->gu_ctl1		= I915_READ(VLV_GU_CTL1);

	s->pcbr			= I915_READ(VLV_PCBR);

	s->clock_gate_dis2	= I915_READ(VLV_GUNIT_CLOCK_GATE2);



	/*
@@ -1189,6 +1190,7 @@ static void vlv_restore_gunit_s0ix_state(struct drm_i915_private *dev_priv) 
	/* Gunit-Display CZ domain, 0x182028-0x1821CF */

	I915_WRITE(VLV_GU_CTL0,			s->gu_ctl0);

	I915_WRITE(VLV_GU_CTL1,			s->gu_ctl1);

	I915_WRITE(VLV_PCBR,			s->pcbr);

	I915_WRITE(VLV_GUNIT_CLOCK_GATE2,	s->clock_gate_dis2);

}
@@ -1197,19 +1199,7 @@ int vlv_force_gfx_clock(struct drm_i915_private *dev_priv, bool force_on) 
	u32 val;

	int err;



	val = I915_READ(VLV_GTLC_SURVIVABILITY_REG);

	WARN_ON(!!(val & VLV_GFX_CLK_FORCE_ON_BIT) == force_on);



#define COND (I915_READ(VLV_GTLC_SURVIVABILITY_REG) & VLV_GFX_CLK_STATUS_BIT)

	/* Wait for a previous force-off to settle */

	if (force_on) {

		err = wait_for(!COND, 20);

		if (err) {

			DRM_ERROR("timeout waiting for GFX clock force-off (%08x)\n",

				  I915_READ(VLV_GTLC_SURVIVABILITY_REG));

			return err;

		}

	}



	val = I915_READ(VLV_GTLC_SURVIVABILITY_REG);

	val &= ~VLV_GFX_CLK_FORCE_ON_BIT;

drivers/gpu/drm/i915/i915_drv.h

+1 −0
Original line number Diff line number Diff line
@@ -1094,6 +1094,7 @@ struct vlv_s0ix_state { 
	/* Display 2 CZ domain */

	u32 gu_ctl0;

	u32 gu_ctl1;

	u32 pcbr;

	u32 clock_gate_dis2;

};