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Commit f340c2ff authored by Deepak M's avatar Deepak M Committed by Jani Nikula
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drm/i915/glk: Add DSI PLL divider range for glk 



PLL divider range for GLK is different than that of
BXT, hence adding the GLK range check in this patch.

v2: Code restructure using min and max ratio variables (Ander)
v3: Code changes to avoid "maybe-uninitialized" warning (Jani)

Signed-off-by: default avatarDeepak M <m.deepak@intel.com>
Signed-off-by: default avatarMadhav Chauhan <madhav.chauhan@intel.com>
Reviewed-by: default avatarJani Nikula <jani.nikula@intel.com>
Signed-off-by: default avatarJani Nikula <jani.nikula@intel.com>
Link: http://patchwork.freedesktop.org/patch/msgid/1487335415-14766-5-git-send-email-madhav.chauhan@intel.com
parent b426f985

drivers/gpu/drm/i915/i915_reg.h

+4 −0
Original line number Diff line number Diff line
@@ -8337,10 +8337,12 @@ enum { 
#define  BXT_DSI_PLL_PVD_RATIO_SHIFT	16

#define  BXT_DSI_PLL_PVD_RATIO_MASK	(3 << BXT_DSI_PLL_PVD_RATIO_SHIFT)

#define  BXT_DSI_PLL_PVD_RATIO_1	(1 << BXT_DSI_PLL_PVD_RATIO_SHIFT)

#define  BXT_DSIC_16X_BY1		(0 << 10)

#define  BXT_DSIC_16X_BY2		(1 << 10)

#define  BXT_DSIC_16X_BY3		(2 << 10)

#define  BXT_DSIC_16X_BY4		(3 << 10)

#define  BXT_DSIC_16X_MASK		(3 << 10)

#define  BXT_DSIA_16X_BY1		(0 << 8)

#define  BXT_DSIA_16X_BY2		(1 << 8)

#define  BXT_DSIA_16X_BY3		(2 << 8)

#define  BXT_DSIA_16X_BY4		(3 << 8)
@@ -8350,6 +8352,8 @@ enum { 


#define BXT_DSI_PLL_RATIO_MAX		0x7D

#define BXT_DSI_PLL_RATIO_MIN		0x22

#define GLK_DSI_PLL_RATIO_MAX		0x6F

#define GLK_DSI_PLL_RATIO_MIN		0x22

#define BXT_DSI_PLL_RATIO_MASK		0xFF

#define BXT_REF_CLOCK_KHZ		19200

drivers/gpu/drm/i915/intel_dsi_pll.c

+17 −7
Original line number Diff line number Diff line
@@ -426,11 +426,12 @@ static void bxt_dsi_program_clocks(struct drm_device *dev, enum port port, 
	I915_WRITE(BXT_MIPI_CLOCK_CTL, tmp);

}



static int bxt_compute_dsi_pll(struct intel_encoder *encoder,

static int gen9lp_compute_dsi_pll(struct intel_encoder *encoder,

			       struct intel_crtc_state *config)

{

	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);

	struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);

	u8 dsi_ratio;

	u8 dsi_ratio, dsi_ratio_min, dsi_ratio_max;

	u32 dsi_clk;



	dsi_clk = dsi_clk_from_pclk(intel_dsi->pclk, intel_dsi->pixel_format,
@@ -442,11 +443,20 @@ static int bxt_compute_dsi_pll(struct intel_encoder *encoder, 
	 * round 'up' the result

	 */

	dsi_ratio = DIV_ROUND_UP(dsi_clk * 2, BXT_REF_CLOCK_KHZ);

	if (dsi_ratio < BXT_DSI_PLL_RATIO_MIN ||

	    dsi_ratio > BXT_DSI_PLL_RATIO_MAX) {



	if (IS_BROXTON(dev_priv)) {

		dsi_ratio_min = BXT_DSI_PLL_RATIO_MIN;

		dsi_ratio_max = BXT_DSI_PLL_RATIO_MAX;

	} else {

		dsi_ratio_min = GLK_DSI_PLL_RATIO_MIN;

		dsi_ratio_max = GLK_DSI_PLL_RATIO_MAX;

	}



	if (dsi_ratio < dsi_ratio_min || dsi_ratio > dsi_ratio_max) {

		DRM_ERROR("Cant get a suitable ratio from DSI PLL ratios\n");

		return -ECHRNG;

	}

	} else

		DRM_DEBUG_KMS("DSI PLL calculation is Done!!\n");



	/*

	 * Program DSI ratio and Select MIPIC and MIPIA PLL output as 8x
@@ -458,7 +468,7 @@ static int bxt_compute_dsi_pll(struct intel_encoder *encoder, 
	/* As per recommendation from hardware team,

	 * Prog PVD ratio =1 if dsi ratio <= 50

	 */

	if (dsi_ratio <= 50)

	if (IS_BROXTON(dev_priv) && dsi_ratio <= 50)

		config->dsi_pll.ctrl |= BXT_DSI_PLL_PVD_RATIO_1;



	return 0;
@@ -518,7 +528,7 @@ int intel_compute_dsi_pll(struct intel_encoder *encoder, 
	if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))

		return vlv_compute_dsi_pll(encoder, config);

	else if (IS_GEN9_LP(dev_priv))

		return bxt_compute_dsi_pll(encoder, config);

		return gen9lp_compute_dsi_pll(encoder, config);



	return -ENODEV;

}