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Commit f2dbad36 authored by Rudolf Marek's avatar Rudolf Marek Committed by Ingo Molnar
Browse files

x86: Make X86_BUG_FXSAVE_LEAK detectable in CPUID on AMD 



[ Note, this is a Git cherry-pick of the following commit:

    2b67799bdf25 ("x86: Make X86_BUG_FXSAVE_LEAK detectable in CPUID on AMD")

  ... for easier x86 PTI code testing and back-porting. ]

The latest AMD AMD64 Architecture Programmer's Manual
adds a CPUID feature XSaveErPtr (CPUID_Fn80000008_EBX[2]).

If this feature is set, the FXSAVE, XSAVE, FXSAVEOPT, XSAVEC, XSAVES
/ FXRSTOR, XRSTOR, XRSTORS always save/restore error pointers,
thus making the X86_BUG_FXSAVE_LEAK workaround obsolete on such CPUs.

Signed-Off-By: default avatarRudolf Marek <r.marek@assembler.cz>
Signed-off-by: default avatarThomas Gleixner <tglx@linutronix.de>
Reviewed-by: default avatarBorislav Petkov <bp@suse.de>
Tested-by: default avatarBorislav Petkov <bp@suse.de>
Cc: Andy Lutomirski <luto@amacapital.net>
Link: https://lkml.kernel.org/r/bdcebe90-62c5-1f05-083c-eba7f08b2540@assembler.cz


Signed-off-by: default avatarIngo Molnar <mingo@kernel.org>
parent a8b4db56

arch/x86/include/asm/cpufeatures.h

+1 −0
Original line number Original line Diff line number Diff line
@@ -266,6 +266,7 @@ 
/* AMD-defined CPU features, CPUID level 0x80000008 (EBX), word 13 */

/* AMD-defined CPU features, CPUID level 0x80000008 (EBX), word 13 */

#define X86_FEATURE_CLZERO		(13*32+ 0) /* CLZERO instruction */

#define X86_FEATURE_CLZERO		(13*32+ 0) /* CLZERO instruction */

#define X86_FEATURE_IRPERF		(13*32+ 1) /* Instructions Retired Count */

#define X86_FEATURE_IRPERF		(13*32+ 1) /* Instructions Retired Count */

#define X86_FEATURE_XSAVEERPTR		(13*32+ 2) /* Always save/restore FP error pointers */





/* Thermal and Power Management Leaf, CPUID level 0x00000006 (EAX), word 14 */

/* Thermal and Power Management Leaf, CPUID level 0x00000006 (EAX), word 14 */

#define X86_FEATURE_DTHERM		(14*32+ 0) /* Digital Thermal Sensor */

#define X86_FEATURE_DTHERM		(14*32+ 0) /* Digital Thermal Sensor */

arch/x86/kernel/cpu/amd.c

+5 −2
Original line number Original line Diff line number Diff line
@@ -804,8 +804,11 @@ static void init_amd(struct cpuinfo_x86 *c) 
	case 0x17: init_amd_zn(c); break;

	case 0x17: init_amd_zn(c); break;

	}

	}





	/* Enable workaround for FXSAVE leak */

	/*

	if (c->x86 >= 6)

	 * Enable workaround for FXSAVE leak on CPUs

	 * without a XSaveErPtr feature

	 */

	if ((c->x86 >= 6) && (!cpu_has(c, X86_FEATURE_XSAVEERPTR)))

		set_cpu_bug(c, X86_BUG_FXSAVE_LEAK);

		set_cpu_bug(c, X86_BUG_FXSAVE_LEAK);





	cpu_detect_cache_sizes(c);

	cpu_detect_cache_sizes(c);