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Commit f267c882 authored by Manuel Lauss's avatar Manuel Lauss Committed by Ralf Baechle
Browse files

MIPS: Alchemy: irq: register pm at irq init time 



No need for a device_initcall.

Signed-off-by: default avatarManuel Lauss <manuel.lauss@googlemail.com>
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/2934/


Signed-off-by: default avatarRalf Baechle <ralf@linux-mips.org>
parent 2a32daf1

arch/mips/alchemy/common/gpioint.c

+38 −36
Original line number Diff line number Diff line
@@ -278,41 +278,7 @@ static int au1300_gpic_settype(struct irq_data *d, unsigned int type) 
	return 0;

}



static void __init alchemy_gpic_init_irq(const struct gpic_devint_data *dints)

{

	int i;

	void __iomem *bank_base;



	mips_cpu_irq_init();



	/* disable & ack all possible interrupt sources */

	for (i = 0; i < 4; i++) {

		bank_base = AU1300_GPIC_ADDR + (i * 4);

		__raw_writel(~0UL, bank_base + AU1300_GPIC_IDIS);

		wmb();

		__raw_writel(~0UL, bank_base + AU1300_GPIC_IPEND);

		wmb();

	}



	/* register an irq_chip for them, with 2nd highest priority */

	for (i = ALCHEMY_GPIC_INT_BASE; i <= ALCHEMY_GPIC_INT_LAST; i++) {

		au1300_set_irq_priority(i, 1);

		au1300_gpic_settype(irq_get_irq_data(i), IRQ_TYPE_NONE);

	}



	/* setup known on-chip sources */

	while ((i = dints->irq) != -1) {

		au1300_gpic_settype(irq_get_irq_data(i), dints->type);

		au1300_set_irq_priority(i, dints->prio);



		if (dints->internal)

			au1300_pinfunc_to_dev(i - ALCHEMY_GPIC_INT_BASE);



		dints++;

	}



	set_c0_status(IE_IRQ0 | IE_IRQ1 | IE_IRQ2 | IE_IRQ3);

}

/******************************************************************************/



static unsigned long alchemy_gpic_pmdata[ALCHEMY_GPIC_INT_NUM + 6];
@@ -383,6 +349,43 @@ static struct syscore_ops alchemy_gpic_pmops = { 
	.resume		= alchemy_gpic_resume,

};



static void __init alchemy_gpic_init_irq(const struct gpic_devint_data *dints)

{

	int i;

	void __iomem *bank_base;



	register_syscore_ops(&alchemy_gpic_pmops);

	mips_cpu_irq_init();



	/* disable & ack all possible interrupt sources */

	for (i = 0; i < 4; i++) {

		bank_base = AU1300_GPIC_ADDR + (i * 4);

		__raw_writel(~0UL, bank_base + AU1300_GPIC_IDIS);

		wmb();

		__raw_writel(~0UL, bank_base + AU1300_GPIC_IPEND);

		wmb();

	}



	/* register an irq_chip for them, with 2nd highest priority */

	for (i = ALCHEMY_GPIC_INT_BASE; i <= ALCHEMY_GPIC_INT_LAST; i++) {

		au1300_set_irq_priority(i, 1);

		au1300_gpic_settype(irq_get_irq_data(i), IRQ_TYPE_NONE);

	}



	/* setup known on-chip sources */

	while ((i = dints->irq) != -1) {

		au1300_gpic_settype(irq_get_irq_data(i), dints->type);

		au1300_set_irq_priority(i, dints->prio);



		if (dints->internal)

			au1300_pinfunc_to_dev(i - ALCHEMY_GPIC_INT_BASE);



		dints++;

	}



	set_c0_status(IE_IRQ0 | IE_IRQ1 | IE_IRQ2 | IE_IRQ3);

}



/**********************************************************************/



void __init arch_init_irq(void)
@@ -390,7 +393,6 @@ void __init arch_init_irq(void) 
	switch (alchemy_get_cputype()) {

	case ALCHEMY_CPU_AU1300:

		alchemy_gpic_init_irq(&au1300_devints[0]);

		register_syscore_ops(&alchemy_gpic_pmops);

		break;

	}

}

arch/mips/alchemy/common/irq.c

+53 −60
Original line number Diff line number Diff line
@@ -510,6 +510,58 @@ static inline void ic_init(void __iomem *base) 
	wmb();

}



static unsigned long alchemy_ic_pmdata[7 * 2];



static inline void alchemy_ic_suspend_one(void __iomem *base, unsigned long *d)

{

	d[0] = __raw_readl(base + IC_CFG0RD);

	d[1] = __raw_readl(base + IC_CFG1RD);

	d[2] = __raw_readl(base + IC_CFG2RD);

	d[3] = __raw_readl(base + IC_SRCRD);

	d[4] = __raw_readl(base + IC_ASSIGNRD);

	d[5] = __raw_readl(base + IC_WAKERD);

	d[6] = __raw_readl(base + IC_MASKRD);

	ic_init(base);		/* shut it up too while at it */

}



static inline void alchemy_ic_resume_one(void __iomem *base, unsigned long *d)

{

	ic_init(base);



	__raw_writel(d[0], base + IC_CFG0SET);

	__raw_writel(d[1], base + IC_CFG1SET);

	__raw_writel(d[2], base + IC_CFG2SET);

	__raw_writel(d[3], base + IC_SRCSET);

	__raw_writel(d[4], base + IC_ASSIGNSET);

	__raw_writel(d[5], base + IC_WAKESET);

	wmb();



	__raw_writel(d[6], base + IC_MASKSET);

	wmb();

}



static int alchemy_ic_suspend(void)

{

	alchemy_ic_suspend_one((void __iomem *)KSEG1ADDR(AU1000_IC0_PHYS_ADDR),

			       alchemy_ic_pmdata);

	alchemy_ic_suspend_one((void __iomem *)KSEG1ADDR(AU1000_IC1_PHYS_ADDR),

			       &alchemy_ic_pmdata[7]);

	return 0;

}



static void alchemy_ic_resume(void)

{

	alchemy_ic_resume_one((void __iomem *)KSEG1ADDR(AU1000_IC1_PHYS_ADDR),

			      &alchemy_ic_pmdata[7]);

	alchemy_ic_resume_one((void __iomem *)KSEG1ADDR(AU1000_IC0_PHYS_ADDR),

			      alchemy_ic_pmdata);

}



static struct syscore_ops alchemy_ic_syscore_ops = {

	.suspend	= alchemy_ic_suspend,

	.resume		= alchemy_ic_resume,

};



static void __init au1000_init_irq(struct au1xxx_irqmap *map)

{

	unsigned int bit, irq_nr;
@@ -517,6 +569,7 @@ static void __init au1000_init_irq(struct au1xxx_irqmap *map) 


	ic_init((void __iomem *)KSEG1ADDR(AU1000_IC0_PHYS_ADDR));

	ic_init((void __iomem *)KSEG1ADDR(AU1000_IC1_PHYS_ADDR));

	register_syscore_ops(&alchemy_ic_syscore_ops);

	mips_cpu_irq_init();



	/* register all 64 possible IC0+IC1 irq sources as type "none".
@@ -573,63 +626,3 @@ void __init arch_init_irq(void) 
		break;

	}

}
 




static unsigned long alchemy_ic_pmdata[7 * 2];



static inline void alchemy_ic_suspend_one(void __iomem *base, unsigned long *d)

{

	d[0] = __raw_readl(base + IC_CFG0RD);

	d[1] = __raw_readl(base + IC_CFG1RD);

	d[2] = __raw_readl(base + IC_CFG2RD);

	d[3] = __raw_readl(base + IC_SRCRD);

	d[4] = __raw_readl(base + IC_ASSIGNRD);

	d[5] = __raw_readl(base + IC_WAKERD);

	d[6] = __raw_readl(base + IC_MASKRD);

	ic_init(base);		/* shut it up too while at it */

}



static inline void alchemy_ic_resume_one(void __iomem *base, unsigned long *d)

{

	ic_init(base);



	__raw_writel(d[0], base + IC_CFG0SET);

	__raw_writel(d[1], base + IC_CFG1SET);

	__raw_writel(d[2], base + IC_CFG2SET);

	__raw_writel(d[3], base + IC_SRCSET);

	__raw_writel(d[4], base + IC_ASSIGNSET);

	__raw_writel(d[5], base + IC_WAKESET);

	wmb();



	__raw_writel(d[6], base + IC_MASKSET);

	wmb();

}



static int alchemy_ic_suspend(void)

{

	alchemy_ic_suspend_one((void __iomem *)KSEG1ADDR(AU1000_IC0_PHYS_ADDR),

			       alchemy_ic_pmdata);

	alchemy_ic_suspend_one((void __iomem *)KSEG1ADDR(AU1000_IC1_PHYS_ADDR),

			       &alchemy_ic_pmdata[7]);

	return 0;

}



static void alchemy_ic_resume(void)

{

	alchemy_ic_resume_one((void __iomem *)KSEG1ADDR(AU1000_IC1_PHYS_ADDR),

			      &alchemy_ic_pmdata[7]);

	alchemy_ic_resume_one((void __iomem *)KSEG1ADDR(AU1000_IC0_PHYS_ADDR),

			      alchemy_ic_pmdata);

}



static struct syscore_ops alchemy_ic_syscore_ops = {

	.suspend	= alchemy_ic_suspend,

	.resume		= alchemy_ic_resume,

};



static int __init alchemy_ic_pm_init(void)

{

	register_syscore_ops(&alchemy_ic_syscore_ops);

	return 0;

}

device_initcall(alchemy_ic_pm_init);