Donate to e Foundation | Murena handsets with /e/OS | Own a part of Murena! Learn more

Commit f1d3d34d authored by Damien Lespiau's avatar Damien Lespiau Committed by Daniel Vetter
Browse files

drm/i915/skl: Fix WaDisableChickenBitTSGBarrierAckForFFSliceCS 



Robert noticed that the FF_SLICE_CS_CHICKEN2 offset was wrong. Ooops.

Ville noticed that the write was wrong since FF_SLICE_CS_CHICKEN2 is a
masked register. Re-oops.

A wonder if went through 2 people while having roughly a bug per line...

The problem was introduced in the original patch:

  commit 2caa3b26
  Author: Damien Lespiau <damien.lespiau@intel.com>
  Date:   Mon Feb 9 19:33:20 2015 +0000

      drm/i915/skl: Implement WaDisableChickenBitTSGBarrierAckForFFSliceCS

v2: Also fix the register write (Ville)

Reported-by: default avatarRobert Beckett <robert.beckett@intel.com>
Reported-by: default avatarVille Syrjälä <ville.syrjala@linux.intel.com>
Cc: Robert Beckett <robert.beckett@intel.com>
Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
Cc: Nick Hoath <nicholas.hoath@intel.com>
Signed-off-by: default avatarDamien Lespiau <damien.lespiau@intel.com>
Reviewed-by: default avatarVille Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: default avatarDaniel Vetter <daniel.vetter@ffwll.ch>
parent 22e02c0b

drivers/gpu/drm/i915/i915_reg.h

+1 −1
Original line number Diff line number Diff line
@@ -5718,7 +5718,7 @@ enum skl_disp_power_wells { 
#define HSW_NDE_RSTWRN_OPT	0x46408

#define  RESET_PCH_HANDSHAKE_ENABLE	(1<<4)



#define FF_SLICE_CS_CHICKEN2			0x02e4

#define FF_SLICE_CS_CHICKEN2			0x20e4

#define  GEN9_TSG_BARRIER_ACK_DISABLE		(1<<8)



/* GEN7 chicken */

drivers/gpu/drm/i915/intel_pm.c

+1 −2
Original line number Diff line number Diff line
@@ -88,8 +88,7 @@ static void skl_init_clock_gating(struct drm_device *dev) 


		/* WaDisableChickenBitTSGBarrierAckForFFSliceCS:skl */

		I915_WRITE(FF_SLICE_CS_CHICKEN2,

			   I915_READ(FF_SLICE_CS_CHICKEN2) |

			   GEN9_TSG_BARRIER_ACK_DISABLE);

			   _MASKED_BIT_ENABLE(GEN9_TSG_BARRIER_ACK_DISABLE));

	}



	if (INTEL_REVID(dev) <= SKL_REVID_E0)